TS8388BVFS datasheet(9/57 Pages) ATMEL

9 / 57 page

TS8388B

2144C–BDC–04/03

Notes:

1. Differential output buffers are internally loaded by 75

Ω resistors. Buffer bias current = 11 mA.

2. See “Definition of Terms” on page 48.

3. Histogram testing based on sampling of a 10 MHz sinewave at 50 MSPS.

4. Output error amplitude < ± 4 lsb around correct code (including gain and offset error).

5. Maximum jitter value obtained for single-ended clock input on the JTS8388B die (chip on board): 200 fs. (500 fs expected on

TS8388BG)

6. Digital output back termination options depicted in Application Notes.

7. With a typical value of TD = 465 ps, at 1 GSPS, the timing safety margin for the data storing using the ECLinPS 10E452 out-

put registers from Motorola® is of ± 315 ps, equally shared before and after the rising edge of the Data Ready signals (DR,

DRB).

8. The clock inputs may be indifferently entered in differential or single-ended, using ECL levels or 4 dBm typical power level

into the 50

Ω termination resistor of the inphase clock input. (4 dBm into 50Ω clock input correspond to 10 dBm power level

for the clock generator.)

9. At 1 GSPS, 50/50 clock duty cycle, TC2 = 500 ps (TC1). TDR - TOD = -100 ps (typ) does not depend on the sampling rate.

10.

Specified loading conditions for digital outputs:

- 50

Ω or 75Ω controlled impedance traces properly 50/75Ω terminated, or unterminated 75Ω controlled impedance traces.

- Controlled impedance traces far end loaded by 1 standard ECLinPS register from Motorola. (i.e.: 10E452) (Typical input

parasitic capacitance of 1.5 pF including package and ESD protections.)

11.

Termination load parasitic capacitance derating values:

- 50

Ω or 75Ω controlled impedance traces properly 50/75Ω terminated: 60 ps/pF or 75 ps per additionnal ECLinPS load.

- Unterminated (source terminated) 75

Ω controlled impedance lines: 100 ps/pF or 150 ps per additionnal ECLinPS termina-

tion load.

12. Apply proper 50/75

Ω impedance traces propagation time derating values: 6 ps/mm (155 ps/inch) for TSEV8388B Evaluation

Board.

13. Values for TOD and TDR track each other over temperature, (1% variation for TOD-TDR per 100

°C temperature variation).

Therefore TOD-TDR variation over temperature is negligible. Moreover, the internal (on-chip) and package skews between

each Data TODs and TDR effect can be considered as negligible. Consequently, minimum values for TOD and TDR are

never more than 100 ps apart. The same is true for the TOD and TDR maximum values (see Advanced Application Notes

about “TOD-TDR Variation Over Temperature” on page 27).

14. Min value guarantees performance. Max value guarantees functionality.

15. Min value guarantees functionality. Max value guarantees performance.

Data ready output delay

TDR

1110

1320

1620

(2)(10)

(11)(12)

Data ready reset delay

TRDR

–

720

1000

Data to data ready – Clock low pulse width

(See “Timing Diagrams” on page 10.)

TOD-TDR

(9)(13)

(14)

Data to data ready output delay (50% duty cycle)

at 1 GSPS (See “Timing Diagrams” on page 10.)

TD1

420

460

500

(2)(15)

Data pipeline delay

TPD

clock

cycles

Table 3. Electrical Specifications (Continued)

Parameter

Symbol

Test

Level

Value

Unit

Note

Min

Typ

Max

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