TS8388BVFS datasheet(7/57 Pages) ATMEL

7 / 57 page

TS8388B

2144C–BDC–04/03

Gain error drift

Offset error drift

–

100

125

150

ppm/

°C

ppm/

°C

DC Accuracy (CQFP68 package)

Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format

Tj (typical) = 70

°C.

Differential non linearity

DNL-

1, 2

-0.5

-0.6

-0.25

-0.35

–

lsb

(2)(3)

Differential non linearity

DNL+

1, 2

–

0.3

0.4

0.6

0.7

lsb

Integral non linearity

INL-

1, 2

-1.0

-1.2

0.7

0.9

–

lsb

(2)(3)

Integral non linearity

INL+

1, 2

–

0.7

0.9

1.0

1.2

lsb

No missing code

–

Guaranteed over specified temperature range

(3)

Gain error

–

1, 2

-10

-11

-2

% FS

% F

Input offset voltage

–

1, 2

-26

-30

-5

Gain error drift

Offset error drift

–

100

125

150

ppm/

°C

ppm/

°C

Transient Performance

Bit Error Rate

FS = 1 GSPS FIN = 62.5 MHz

BER

–

1E-12

Error/

sample

(2)(4)

ADC settling time

VIN -VINB = 400 mVpp

–

0.5

(2)

Overvoltage recovery time

TOR

–

0.5

(2)

AC Performance

Single-ended or differential input and clock mode, 50% clock duty cycle (CLK, CLKB), Binary output data format,

Tj = 70

°C, unless otherwise specified.

Signal to Noise and Distortion ratio

SINAD

–

–––

–

(2)

S = 1 GSPS, FIN = 20 MHz

–

FS = 1 GSPS, FIN = 500 MHz

–

S = 1 GSPS, FIN = 1000 MHz (-1 dBFs)

–

S = 50 MSPS, FIN = 25 MHz

1, 2, 6

–

Table 3. Electrical Specifications (Continued)

Parameter

Symbol

Test

Level

Value

Unit

Note

Min

Typ

Max

TS8388BVFS Datasheet(PDF) 7 Page - ATMEL Corporation

TS8388BVFS Datasheet(HTML) 7 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57

Datasheet Download

Link URL