TS8388BVFS datasheet(30/57 Pages) ATMEL

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TS8388B

2144C–BDC–04/03

Differential Versus

Single-ended Analog

Input Operation

The TS8388B can operate at full speed in either differential or single-ended configuration.

This is explained by the fact the ADC uses a high input impedance differential preamplifier

stage, (preceeding the Sample and hold stage), which has been designed in order to be

entered either in differential mode or single-ended mode.

This is true so long as the out-of-phase analog input pin V

INB is 50Ω terminated very closely to

one of the neighboring shield ground pins (52, 53, 58, 59) which constitute the local ground

reference for the inphase analog input pin (V

IN).

Thus the differential analog input preamplifier will fully reject the local ground noise (and any

capacitively and inductively coupled noise) as common mode effects.

In typical single-ended configuration, enter on the (V

IN) input pin, with the inverted phase input

pin (V

INB) grounded through the 50Ω termination resistor.

In single-ended input configuration, the in-phase input amplitude is 0.5V peak to peak, cen-

tered on 0V (or -2 dBm into 50

Ω). The inverted phase input is at ground potential through a

Ω termination resistor.

However, dynamic performances can be somewhat improved by entering either analog or

clock inputs in differential mode.

Typical Single-ended

Analog Input

Configuration

Figure 30. Typical Single-ended Analog Input Configuration

Note:

Since VIN and VINB have a double pad architecture, a 50

Ω reverse termination is needed. For the CBGA package, this reverse

termination is already on package.

Clock Inputs (CLK)

(CLKB)

The TS8388B can be clocked at full speed without noticeable performance degradation in

either differential or single-ended configuration.

This is explained by the fact the ADC uses a differential preamplifier stage for the clock buffer,

which has been designed in order to be entered either in differential or single-ended mode.

Recommended sinewave generator characteristics are typically -120 dBc/Hz phase noise floor

spectral density, at 1 kHz from carrier, assuming a single tone 4 dBm input for the clock signal.

Single-ended Clock

Input (Ground

Common Mode)

Although the clock inputs were intended to be driven differentially with nominal -0.8V/-1.8V

ECL levels, the TS8388B clock buffer can manage a single-ended sinewave clock signal cen-

tered around 0V. This is the most convenient clock input configuration as it does not require

the use of a power splitter.

Ω

(external or

on package)

1 M

Ω

3 pF

-250

250

500 mV

[mV]

VIN

VIN =

±250 mV = 500 mV diff

VIN or VINB double pad (pins 54, 55 or 56, 57)

VIN or VINB

Ω reverse termination

500 mV

Full Scale

analog input

VINB = 0V

VINB

TS8388BVFS Datasheet(PDF) 30 Page - ATMEL Corporation

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