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HT45F3520 Datasheet(PDF) 47 Page - Holtek Semiconductor Inc |
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HT45F3520 Datasheet(HTML) 47 Page - Holtek Semiconductor Inc |
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47 / 134 page  Rev. 1.10 4� De�e��e� 1�� �01� Rev. 1.10 47 De�e��e� 1�� �01� HT45F3520/HT45F3530 Personal Care Flash MCU HT45F3520/HT45F3530 Personal Care Flash MCU Bit2 LVRF:LVRfunctionresetflag Describeelsewhere Bit1 Unimplemented,readas"0" Bit0 WRF:WDTControlregistersoftwareresetflag 0:Notoccur 1:Occurred Thisbitissetto1bytheWDTControlregistersoftwareresetandclearedbythe applicationprogram.Notethatthisbitcanonlybeclearedto0bytheapplication program. Watchdog Timer Operation TheWatchdogTimeroperatesbyprovidingadeviceresetwhenitstimeroverflows.Thismeans thatintheapplicationprogramandduringnormaloperationtheuserhastostrategicallyclearthe WatchdogTimerbeforeitoverflowstopreventtheWatchdogTimerfromexecutingareset.Thisis doneusingtheclearwatchdoginstructions.Iftheprogrammalfunctionsforwhateverreason,jumps toanunknownlocation,orentersanendlessloop,theclearWDTinstructionswillnotbeexecuted inthecorrectmanner,inwhichcasetheWatchdogTimerwilloverflowandresetthedevice.The WatchdogTimerisalwaysenabled,buttherearefivebits,WE4~WE0,intheWDTCregistertogive additionalcontroloftheWatchdogTimer. WE4 ~ WE0 Bits WDT Function 01010B o� 10101B Ena�le Any othe� value Reset MCU Watchdog Timer Enable Control Undernormalprogramoperation,aWatchdogTimertime-outwillinitialiseadeviceresetandset thestatusbitTO.However,ifthesystemisintheSLEEPorIDLEMode,whenaWatchdogTimer time-outoccurs,theTObitinthestatusregisterwillbesethighandonlytheProgramCounterand StackPointerwillbereset.ThreemethodscanbeadoptedtoclearthecontentsoftheWatchdog Timer.ThefirstisaWDTreset,whichmeansavalueotherthan01010Band10101Biswritteninto theWE4~WE0bitlocations,thesecondisusingtheWatchdogTimersoftwareclearinstructionsand thethirdisviaaHALTinstruction.Thereisonlyonemethodofusingsoftwareinstructiontoclear theWatchdogTimer.Thatistousethesingle"CLRWDT"instructiontocleartheWDT. Themaximumtime-outperiodiswhenthe215divisionratioisselected.Asanexample,witha 32kHzLIRCoscillatorasitssourceclock,thiswillgiveamaximumwatchdogperiodofaround1 secondforthe215divisionratio,andaminimumtimeoutof8msforthe28divisionration. “ CLR WDT”Inst�u�tion 11-stage Divide� 7-stage Divide� WE4~WE0 �its WDTC Registe� Reset MCU fLIRC 8-to-1 MUX CLR WS�~WS0 WDT Ti�e-out (�8/fLIRC ~ �15/fLIRC) LIRC “ HALT”Inst�u�tion Watchdog Timer |
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