RX231 datasheet(12/177 Pages) RENESAS

12 / 177 page

R01DS0261EJ0110 Rev.1.10

Page 12 of 177

Oct 30, 2015

RX230 Group, RX231 Group

1. Overview

1.3

Block Diagram

Figure 1.2

shows a block diagram.

Figure 1.2

Block Diagram

Clock

generation

circuit

RX CPU

RAM

ROM

Port 0

Port 1

Port 3

Port 4

12-bit D/A converter × 2 channels

RIICa × 1 channel

DOC

RTCe

MTU2a × 6 channels

12-bit A/D converter × 24 channels

CMT × 2 channels (unit 0)

RSPIa × 1 channel

DTCa

ICUb

CAC

SCIh × 1 channel

Port 5

Port A

Port B

Port C

POE2a

USB 2.0 host/function module

Port 2

Temperature sensor

Port D

Port H

Port J

External bus

DMACA

× 4 channels

Comparator B × 4 channels

TMR × 2 channels (unit 0)

TMR × 2 channels (unit 1)

SSI

CMT × 2 channels (unit 1)

MPU

TPUa × 6 channels

BSC

SCIg × 6 channels

(including IrDA × 1 channel)

E2 DataFlash

CRC

ELC

IWDTa

WDTA

SDHIa

RSCAN

CTSU

LPT

Port E

ICUb:

Interrupt controller

DTCa:

Data transfer controller

DMACA:

DMA controller

BSC:

Bus controller

WDTA:

Watchdog timer

IWDTa:

Independent watchdog timer

ELC:

Event link controller

CRC:

CRC (cyclic redundancy check) calculator

SCIg/SCIh: Serial communications interface

RSPIa:

Serial peripheral interface

SSI:

Serial sound interface

RIICa:

I2C bus interface

TPUa:

16-bit timer pulse unit

MTU2a:

Multi-function timer pulse unit 2

POE2a:

Port output enable 2

CMT:

Compare match timer

RTCe:

Realtime clock

DOC:

Data operation circuit

CAC:

Clock frequency accuracy measurement circuit

CTSU:

Capacitive touch sensing unit

SDHIa:

SD host interface

MPU:

Memory protection unit

TMR:

8-bit timer

RSCAN:

CAN module

LPT:

Low power timer

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