FDC37M604 datasheet(21/182 Pages) SMSC

21 / 182 page

DATA RATE SELECT REGISTER (DSR)

Address 3F4 WRITE ONLY

This register is write only. It is used to program

the data rate, amount of write precompensation,

power down status, and software reset.

The

data

rate

programmed

using

the

Configuration Control Register (CCR) not

the

DSR,

for

PC/AT

and

PS/2

Model

and

Microchannel

applications.

Other

applications can set the data rate in the DSR.

The data rate of the floppy controller is the most

recent write of either the DSR or CCR. The DSR

is unaffected by a software reset. A hardware

reset

will

set

the

DSR

02H,

which

corresponds to the default precompensation

setting and 250 Kbps.

BIT 0 and 1 DATA RATE SELECT

These bits control the data rate of the floppy

controller.

See Table 11 for the settings

corresponding to the individual data rates. The

data rate select bits are unaffected by a

software reset, and are set to 250 Kbps after a

hardware reset.

BIT

through

PRECOMPENSATION

SELECT

These three bits select the value of write

precompensation that will be applied to the

WDATA output signal.

Table 10 shows the

precompensation values for the combination of

these bits settings.

Track 0 is the default

starting track number to start precompensation.

this starting track number can be changed by

the configure command.

BIT 5 UNDEFINED

Should be written as a logic "0".

BIT 6 LOW POWER

A logic "1" written to this bit will put the floppy

controller into manual low power mode. The

floppy controller

clock

and data Note: The

DSR is Shadowed in the Floppy Data Rate

Select

Shadow

LD8:CRC2[7:0],

separator circuits will be turned off.

The

controller will come out of manual low power

mode after a software reset or access to the

Data Register or Main Status Register.

BIT 7 SOFTWARE RESET

This active high bit has the same function as the

DOR RESET (DOR bit 2) except that this bit is

self clearing.

Table 10 - Precompensation Delays

S/W

RESET

POWER

DOWN

PRE-

COMP2

PRE-

COMP1

PRE-

COMP0

DRATE

SEL1

DRATE

SEL0

RESET

COND.

PRECOMP

432

PRECOMPENSATION DELAY

(nsec)

<2Mbps

2Mbps*

111

001

010

011

100

101

110

000

0.00

41.67

83.34

125.00

166.67

208.33

250.00

Default

20.8

41.7

62.5

83.3

104.2

125

Default

Default: See Table 12

*2Mbps data rate is only available if Vcc= 5V.

FDC37M604 Datasheet(PDF) 21 Page - SMSC Corporation

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