AMD

2-355

PALCE29MA16H-25

SOME POSSIBLE CONFIGURATIONS OF THE INPUT/OUTPUT LOGIC MACROCELL

(For other useful configurations, please refer to the macrocell diagrams in Figure 2. All macrocell architecture cells are

independently programmable).

DQ

Q

S = 1

S = 0

S = 1

S = 1

0

1

3

2

Output Registered/Active Low

DQ

Q

S = 1

S = 1

S = 1

0

1

3

Output Combinatorial/Active Low

DQ

Q

S = 0

S = 0

S = 1

S = 1

0

1

3

2

Output Registered/Active High

DQ

Q

S = 0

S = 1

S = 1

0

1

3

Output Combinatorial/Active High

08811G-6

08811G-7

08811G-8

08811G-9

Figure 3a. Dual Feedback Macrocells

DQ

S = 1

S = 0

S = 1

S = 0

S = 1

0

1

3

8

2

Q

Output Registered/Active Low, I/O Feedback

S = 1

S = 1

S = 1

S = 0

0

1

3

8

Output Combinatorial/Active Low, I/O Feedback

DQ

LE

S = 0

S = 0

S = 1

S = 0

S = 0

0

1

3

8

2

Q

Output Latched/Active High, I/O Feedback

S = 0

S = 1

S = 1

S = 0

0

1

3

8

Output Combinatorial/Active High, I/O Feedback

08811G-10

08811G-11

08811G-12

08811G-13

Figure 3b. Single Feedback Macrocells