BT856 datasheet(23/54 Pages) ETC

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CIRCUIT DESCRIPTION

Pixel Input Ranges and Colorspace Conversion

Bt856/7

YC Inputs (4:2:2 YCrCb)

Y has a nominal range of 16–235; Cb and Cr have a nominal range of 16–240, with

128 equal to zero. Values of 0 and 255 are interpreted as 1 and 254, respectively. Y

values of 1–15 and 236–254, and CrCb values of 1–15 and 241–254, are interpret-

ed as valid linear values.

Alternatively, software bit D5 of register 0xDC can alter pixel scaling and dis-

able or enable the 7.5 IRE setup. When this bit is enabled, PAL–B, D, G, H, I, N,

N-Argentina video can be generated using NTSC/PAL–M blanking levels and 7.5

IRE setup, and NTSC/PAL–M pixel scaling is performed (Y range of 16-235 rep-

resents 7.5-100 IRE); or, NTSC/PAL–M video can be generated using PAL–B, D,

G, H, I, N, N-Argentina scaling (Y range of 16-235 represents 0-100 IRE) without

the 7.5 IRE setup. NTSC/PAL–M mode with setup disabled has 2% less

black-to-white range than NTSC/PAL–M mode with setup enabled.

For RGBOUT mode, 4:2:2 YCrCb digital component video will be used to gen-

erate composite video and will be converted to the RGB colorspace to drive the

RGB DACs. The Y input range of 16–235 will produce a range of 0.7 V at the out-

put. Since YC values outside of the nominal range are allowed, the black level is

raised above zero volts to allow for Y values less than 16, and the output range of

the DACs can exceed 0.7 V to allow for Y values above 235. The conversion is lin-

early scaled in the overshoot and undershoot regions. The following matrix, based

on CCIR 601, is used to convert YCrCb to RGB:

R = Y + 1.371*Cr

G = Y – 0.699*Cr – 0.337*Cb

B = Y + 1.733*Cb

Values are rounded to 9-bits at the DAC.

An averaging interpolation ﬁlter is available to upsample the RGB pixel stream.

Upsampling is enabled or disabled in either of two ways: with the GAMMA* pin

or with software bit D2 of register 0xDA. The pin-override switch (bit D4 of reg-

ister 0xDC) determines which method has priority: if the override is high, then

software is used; if the override is low, then the GAMMA* pin is used. In both cas-

es (GAMMA* pin or bit D2 of register 0xDA), a logical low enables upsampling

and a logical high disables upsampling. The pipeline delay is the same regardless

of whether upsampling is active or not (please see AC Characteristics for pipeline

delay).

DAC Coding

White is represented by a DAC code of 400. For PAL–B, D, G, H, I, N, N-Argen-

tina, the standard blanking level is represented by a DAC code of 120. For

NTSC/PAL–M, with setup enabled (bit D5 of register 0xDC is ‘0’), the standard

blanking level is represented by a DAC code of 114, 1 IRE is equivalent to a DAC

code of 2.857. For NTSC/PAL–M with setup disabled (bit D5 of register 0xDC is

‘1’), the standard blanking level is represented by a DAC code of 112, 1 IRE is

equivalent to a DAC code of 2.800.

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