BT856 datasheet(12/54 Pages) ETC

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Brooktree®

CIRCUIT DESCRIPTION

Clock Timing

Bt856/7

Clock Timing

Both CLKX1 and CLKX2 must be supplied to Bt856/7. The internal CLOCK is

derived by registering inverted CLKX1 with the rising edge of CLKX2. Synchro-

nous inputs and outputs are registered by the rising edge of CLOCK, except in

8-bit YCrCb input mode where Cb/Cr are registered on the falling edge of

CLOCK. The timing parameters speciﬁed under AC Characteristics in the Para-

metric Information section are deﬁned with respect to CLKX2. Inputs must be val-

id for the minimum speciﬁed setup time prior to the rising edge of CLKX2 while

CLKX1 is low (except in 8-bit YCrCb mode where Cb/Cr are registered while

CLKX1 is high).

Pixel Input Timing

24-bit RGB Input Mode

R0–R7, G0–G7, B0–B7 are registered on the rising edge of CLOCK. This mode is

enabled by setting the YCMODE pin low.

16-bit YCrCb Input Mode

This mode is available by setting the YCMODE pin high. Y0–Y7 data is input via

the G0–G7 inputs; multiplexed Cb0–Cb7 and Cr0–Cr7 data is input via the B0–B7

inputs. G0–G7 and B0–B7 are registered on the rising edge of CLOCK. R0–R7

and GAMMA* pins are ignored.

8-bit YCrCb Input Mode

The 8-bit YCrCb multiplexed input mode is selected by setting the YCMODE pin

high and by setting register bit D7 of register 0xDC to a 1. Multiplexed Y, Cb, and

Cr data is input through the G0–G7 inputs or through the B0–B7 inputs. The

GAMMA* pin is used to select between the two different 8-bit ports: if GAMMA*

is high, YCrCb is input through B0–B7; if GAMMA* is low, YCrCb is input

through G0–G7. By default, the input sequence for active video pixels must be

Cb0, Y0, Cr0, Y1, Cb2, Y2, Cr2, Y3, etc. in accordance with CCIR656.

Y and Cb/Cr are registered during a single CLOCK period. Cb or Cr is regis-

tered ﬁrst, on the falling edge of CLOCK; Y is registered next, on the rising edge

of CLOCK.

CBFLAG Timing

By default, Cb data is input during odd (base1) values of the horizontal counter

while Cr data is registered during even counts. Cb data may be input during even

values of the horizontal counter by writing a 1 to register bit D6 of register 0xDC.

The falling edge of HSYNC* corresponds to a horizontal count of one (default af-

ter RESET* cycle) unless the Bt856/7 is conﬁgured in master mode with program-

mable HSYNC* output timing.

BT856 Datasheet(PDF) 12 Page - List of Unclassifed Manufacturers