BT856 datasheet(41/54 Pages) ETC

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Brooktree®

PC BOARD CONSIDERATIONS

Decoupling

Bt856/7

Decoupling

Device Decoupling

For optimum performance, all capacitors should be located as close as possible to

the device, and the shortest possible leads (consistent with reliable operation)

should be used to reduce the lead inductance. Chip capacitors are recommended

for minimum lead inductance. Radial lead ceramic capacitors may be substituted

for chip capacitors and are better than axial lead capacitors for self-resonance. Val-

ues are chosen to have self-resonance above the pixel clock.

Power Supply

Decoupling

The best power supply performance is obtained with a 0.1

µF ceramic capacitor

decoupling each group of VAA pins to GND. The capacitors should be placed as

close as possible to the device VAA and GND pins and connected with short, wide

traces.

The 47

µF capacitor shown in Figures 15 and 16 is for low-frequency power

supply ripple; the 0.1

µF capacitors are for high-frequency power supply noise

rejection.

When a linear regulator is used, the power-up sequence must be veriﬁed to pre-

vent latchup. A linear regulator is recommended to ﬁlter the analog power supply

if the power supply noise is greater than or equal to 200 mV. This is especially im-

portant when a switching power supply is used, and the switching frequency is

close to the raster scan frequency. About 5% of the power supply hum and ripple

noise less than 1 MHz will couple onto the analog outputs.

COMP Decoupling

The COMP pin must be decoupled to VAA pin 66, typically with a 0.1

µF ceramic

capacitor. Low-frequency supply noise will require a larger value. The COMP ca-

pacitor must be as close as possible to the COMP and VAA pins. A surface-mount

ceramic chip capacitor is preferred for minimal lead inductance. Lead inductance

degrades the noise rejection of the circuit. Short, wide traces will also reduce lead

inductance.

VREF _IN Decoupling

A 0.1

µF ceramic capacitor should be used to decouple this input to GND.

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