BT856 datasheet(46/54 Pages) ETC

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PC BOARD CONSIDERATIONS

I2C Programming

Bt856/7

I2C Programming

Data Transfer on

the I2C Bus

Figure 17 shows the relationship between IIC DATA and IIC CLOCK to be used

when programming the I2C bus. If the bus is not being used, both IIC DATA and

IIC CLOCK lines must be left high.

Every byte put onto the IIC DATA line should be 8 bits long (MSB ﬁrst), fol-

lowed by an acknowledge bit, which is generated by the receiving device.

Each data transfer is initiated with a start condition and ended with a stop con-

dition. The ﬁrst byte after a start condition is always the address byte. If this is the

device’s own address, the device will generate an acknowledge by pulling the IIC

DATA line low during the ninth clock pulse, then accept the data in subsequent

bytes (autoincrementing the subaddress) until another stop condition is detected.

The eighth bit of the address byte is the read/write bit (high = read from ad-

dressed device, low = write to the addressed device) so, for the Bt856/7, the ad-

dress is only considered valid if the R/W bit is low.

Data bytes are always acknowledged during the ninth clock pulse by the ad-

dressed device. Note that during the acknowledge period the transmitting device

must leave the IIC DATA line high.

Premature termination of the data transfer is allowed by generating a stop con-

dition at any time. When this happens, the Bt856/7 will remain in the state deﬁned

by the last complete data byte transmitted. Any master acknowledge subsequent to

reading the chip ID (subaddress 0x89) is ignored.

Figure 17. IIC Diagram

Note 1:

Acknowledge generated by Bt856/7.

IIC CLOCK

456

234

Subsequent Bytes and Acknowledge

Interpreted as Data Values for

Autoincremented Subaddress Locations

IIC DATA

(Note 1)

SUBADDRESS

(XX)

DATA

(XX)

MAIN ADDRESS

(XX)

(Note 1)

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