prel

imin

ary

prel

imin

ary

iC-MB4

BiSS INTERFACE MASTER

Rev B2, Page 16/40

OPERATING REQUIREMENTS: BiSS Interface (SSI mode)

Operating conditions: register bit SELSSI = 1; VDD = 3. . . 5.5 V, Tj = -40. . . 125 °C

Alias: MA = MA1/MA2_NMA1, SL = SL1/SL2_NSL1

Item

Symbol

Parameter

Conditions

Unit

No.

Min.

Max.

I501 TMAS

Clock Period

FreqSens via FREQ(4:0) selected in

2

320

1/f(CLK)

accordance with table 45 on page 29

I502 tMASh

Clock Signal Hi Level Duration

50

50

%

TMAS

I503 tMASl

Clock Signal Lo Level Duration

50

50

%

TMAS

I504 tsDC

Setup Time: SL stable before MA lo→hi

30

ns

I505 thDC

Hold Time: SL stable after MA lo→hi

0

ns

Figure 10: Timing diagram SSI mode

SLx line sampling

In SSI interface mode SL1 values are sampled with the rising edge at MA1. An overall delay of the sensor

response to the clock at MA1, caused by process times in the sensor or transmission times, is permissible up to

the length of one clock cycle.