IC-MB4 datasheet(35/40 Pages) ICHAUS

35 / 40 page

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iC-MB4

BiSS INTERFACE MASTER

Rev B2, Page 35/40

STATUS INFORMATION 1

In sensor mode the validity of data is stored sepa-

rately for each slave in the validity message register. In

the event of error the appropriate validity message is

deleted and nSENSERR set to 0 in the status register.

The error is signaled at pin NER.

EOT

Addr. 0xF0; bit 0

R - 1

Data transmission active

Data transmission finished

Table 66: End of transmission

In register mode a register error (nREGERR = 0) or

a slave start signal missed at least 4096 MA1 clock

pulses results in an error message at NER.

REGEND

Addr. 0xF0; bit 2

R - 0

No valid register data available

Table 67: End of register communication

A register watchdog error is also triggered if a slave

response is lacking during the transmission of register

data. This has two possible causes: either a slave does

not respond to the first falling edge with a low or the

slave fails to generate a start bit.

nREGERR

Addr. 0xF0; bit 3

R - 1

Error in last register data transmission

No error in last register data transmission

Table 68: Register communication error

The nREGERR bit is reset by writing BREAK = 1 into in-

struction register 0xF4 or writing INIT = 1 into instruction

number of bytes transmitted correctly before the error

occurred can be determined by reading out the register

message REGBYTES (address 0xF3, bits 5...0). In the

event of error the transmission of data is terminated.

If a sensor data error is signaled the faulty sensor can

be verified by reading out address 0xF1 (validity mes-

sage).

nSCDERR

Addr. 0xF0; bit 4

R - 1

Error in last single cycle data transmission

No error in last single cycle data transmission

Table 69: SCD transmission error

The nSCDERR bit is reset by writing BREAK = 1 into

instruction register 0xF4.

An AGS watchdog error nAGSERR is set during the

automatic transmission of sensor data if no new cycle

could be initiated; bit AGS in the command register is

reset and the automatic request for sensor data aborted.

During the transmission of register data a watchdog er-

ror is triggered if the slave shows no response, i.e. if it

does not answer the first falling master edge with a low

or fails to generate a start bit.

nAGSERR

Addr. 0xF0; bit 6

R - 1

AGS watchdog error

No AGS watchdog error

Table 70: AGS error

The nAGSERR bit is reset by writing into instruction

struction is written into register 0xF4.

It is possible to connect other components to pin NER

which can also generate an error message; this can

then be read out via bit nERR in the status register.

nERR

Addr. 0xF0; bit 7

R - 1

Error

No error

Table 71: Transmission error

nDELAYERR

Addr. 0xF0; bit 5

R - 1

Delay error

No Delay error

Table 72: Delay error

The SVALIDx bit indicates the validity of each slaves

SCD CRC verification. A prior set SVALIDx bit can be

reset by writing 0 into the register.

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