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IC-MB4 Datasheet(PDF) 36 Page - IC-Haus GmbH |
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IC-MB4 Datasheet(HTML) 36 Page - IC-Haus GmbH |
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36 / 40 page ![]() prel imin ary prel imin ary iC-MB4 BiSS INTERFACE MASTER Rev B2, Page 36/40 SVALID1 Addr. 0xF1; bit 1 R/W - 0 SVALID2 Addr. 0xF1; bit 3 R/W - 0 SVALID3 Addr. 0xF1; bit 5 R/W - 0 SVALID4 Addr. 0xF1; bit 7 R/W - 0 SVALID5 Addr. 0xF2; bit 1 R/W - 0 SVALID6 Addr. 0xF2; bit 3 R/W - 0 SVALID7 Addr. 0xF2; bit 5 R/W - 0 SVALID8 Addr. 0xF2; bit 7 R/W - 0 0 SCD invalid 1 SCD valid Table 73: SCDATAx validity indication With BiSS C register communication the count of SCD cycles with CDM = 0 is relevant for a manual register communication by host control. Therefore the CDM- TIMEOUT bit indicates that ≥ 14 SCD cycles with CDM = 0 have been sent before. CDMTIMEOUT (Register vaild) Addr. 0xF3; bit 7 R - 1 0 CDMTIMEOUT not reached 1 CDMTIMEOUT reached Table 74: CDM timeout reached CDSSEL Addr. 0xF3; bit 6 R - 1 CDS from the selected channel Table 75: CDS bit from the selected channel STATUS INFORMATION 2 SL1 Addr. 0xF8; bit 0 R - 1 SL2 Addr. 0xF8; bit 2 R - 1 SL3∗ Addr. 0xF8; bit 4 R - 1 SL4∗ Addr. 0xF8; bit 6 R - 1 SL5∗ Addr. 0xF9; bit 0 R - 1 SL6∗ Addr. 0xF9; bit 2 R - 1 SL7∗ Addr. 0xF9; bit 4 R - 1 SL8∗ Addr. 0xF9; bit 6 R - 1 0 SL line level low 1 SL line level high Table 76: SL input line state CDS1 Addr. 0xF8; bit 1 R - 1 CDS2 Addr. 0xF8; bit 3 R - 1 CDS3† Addr. 0xF8; bit 5 R - 1 CDS4† Addr. 0xF8; bit 7 R - 1 CDS5† Addr. 0xF9; bit 1 R - 1 CDS6† Addr. 0xF9; bit 3 R - 1 CDS7† Addr. 0xF9; bit 5 R - 1 CDS8† Addr. 0xF9; bit 7 R - 1 0 CDS = 0 1 CDS = 1 Table 77: CDS bit of channel SWBANKFAILS Bank switching SCD not successful Addr. 0xFB; bit 0 R - 1 0 Bank switching (SCD) successful 1 Bank switching (SCD) not successful Table 78: Bank switching status ∗ SL3 . . . SL8 are not available with iC-MB4. † CDS3 . . . CDS8 are not available with iC-MB4. |
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