IC-MB4 datasheet(29/40 Pages) ICHAUS

29 / 40 page

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iC-MB4

BiSS INTERFACE MASTER

Rev B2, Page 29/40

MAFS

Addr. 0xF5; bit 4

R/W

Controlling selected(CHSEL) MA clock line: using

MA signal

Controlling selected(CHSEL) MA clock line: using

MAVS level

Table 40: Selected MA line control selection

MAVS

Addr. 0xF5; bit 5

R/W

Low definition of selected(CHSEL) MA clock lines

High definition of selected(CHSEL) MA clock lines

Table 41: Selected MA line control level

MAFO

Addr. 0xF5; bit 6

R/W

Controlling unselected(CHSEL) MA clock line: using

MA signal

Controlling unselected(CHSEL) MA clock line: using

MAVS level

Table 42: Not selected MA line control selection

MAVO

Addr. 0xF5; bit 7

R/W

Low definition of unselected(CHSEL) MA clock lines

High definition of unselected(CHSEL) MA clock lines

Table 43: Not selected MA line control level

CONFIGURATION MASTER

Master Clock MA

The master clock, either generated by the basic clock

of the internal 20 MHz oscillator (CLKENI = 1) or by an

external clock oscillator (CLKENI = 0) which supplies

pin CLK, is set with the aid of the frequency division

The MA clock frequency for both BiSS and SSI modes

is set via FREQ(4:0) in accordance with table 44. With

an external clock pulse of f(CLK) = 20 MHz clock fre-

quencies ranging from 62.5 kHz to 10 MHz can thus be

selected for sensor data transmission.

FREQS

Addr. 0xE6; bit 4:0

R/W

0x00

fCLK/ 2

0x01

fCLK/ 4

0x02

fCLK/ 6

0x03

fCLK/ 8

. . .

0x09

fCLK/ 20

. . .

0x0D

fCLK/ 28

0x0E

fCLK/ 30

0x0F

fCLK/ 32

0x10

”not permitted”

0x11

fCLK/ 40

0x12

fCLK/ 60

0x13

fCLK/ 80

. . .

0x1D

fCLK/ 280

0x1E

fCLK/ 300

0x1F

fCLK/ 320

Table 44: Sensor data clock frequency

Both BiSS and SSI devices recognize an idle bus at

the end of a transmission cycle via a monoflop timeout

elapsing (timeoutSENS, see BiSS protocol). The choice

of possible clock frequencies is thus limited as the du-

ration of both the high and low level may not exceed

the shortest timeout of all of the connected subscribers

(slaves).

BiSS B devices switch to register mode when recogniz-

ing that the bus is idle after a high-low transition at the

clock input and signal this state back to the master on

the data line.

The clock frequency in BiSS B register mode is set via

parameter FREQ and within a range of 244 Hz to 5 MHz.

The selection is also limited as a different monoflop

timeout does now recognize the idle bus at the end of

the cycle (timeoutREG, see BiSS B protocol).

FREQR

Addr. 0xE6; bit 7:5

R/W

0 . .

FreqSens/ (2 * (FREQ(7:5)+1) )

FreqSens / 2

FreqSens / 4

FreqSens / 8

FreqSens / 16

FreqSens / 32

FreqSens / 64

FreqSens / 128

FreqSens / 256

Table 45: BiSS B register data frequency

BiSS B devices typically require a minimum clock fre-

quency (such as 250 kHz) due to the MA clock form

has to be evaluated as a possible PWM signal for regis-

ter communication. BiSS C devices generally permit a

lower clock frequency. BiSS C devices do not use the

MA clock duty cycle (PWM signal) and can be operated

down to 80 kHz. SSI devices generally permit a lower

clock frequency and with extended SSI the register ac-

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