AD9208 datasheet(39/137 Pages) AD

39 / 137 page

AD9208

Data Sheet

Rev. 0 | Page 38 of 136

PROGRAMMING INSTRUCTIONS

Use the following procedure to set up the programmable FIR filter:

Enable the sample clock to the device.

Configure the mode registers as follows:

Set the device index to Channel A (I path)

(Register 0x0008 = 0x01).

Set the I path mode (I mode) and gain in

and Table 13).

Set the device index to Channel B (Q path)

(Register 0x0008 = 0x02).

Set the Q path mode (Q mode) and gain in

Wait at least 5 μs to allow the programmable filter to power up.

Program the I path coefficients to the internal shadow

registers as follows:

Set the device index to Channel A (I path)

(Register 0x0008 = 0x01).

Program the XI coefficients in Register 0x0E00 to

Program the YI coefficients in Register 0x0F00 to

Program the tapped delay in Register 0x0F30 (note

that this step is optional).

Program the Q path coefficients to the internal shadow

registers as follows:

Set the device index to Channel B (Q path)

(Register 0x0008 = 0x02).

Set the Q path mode and gain in Register 0x0DF8 and

Program the XQ coefficients in Register 0x0E00 to

Program the YQ coefficients in Register 0x0F00 to

Program the tapped delay in Register 0x0F30 (note

that this step is optional).

Set the chip transfer bit using either of the following

methods (note that setting the chip transfer bit applies the

programmed shadow coefficients to the filter):

Via the register map using the write the chip transfer

bit (Register 0x000F = 0x01).

Via a GPIO pin, as follows:

Configure one of the GPIO pins as the chip

transfer bit in Register 0x0040 to Register 0x0042.

ii.

Toggle the GPIO pin to initiate the chip transfer

(the rising edge is triggered).

When the I or Q path mode register changes in

Table 12. Register 0x0DF8 Definition

Bit(s)

Description

[7:3]

Reserved

[2:0]

Filter mode (I mode or Q mode)

000: filters bypassed

001: real 24-tap filter (X only)

010: real 48-tap filter (X and Y together)

100: real set of two cascaded 24-tap filters (X then Y

cascaded)

101: full complex filter using four real 24-tap filters for the

A/B channels (opposite channel must also be set to 101)

110: half complex filter using two real 48-tap filters +

48-tap delay line (X and Y together) (opposite channel

must also be set to 010)

111: real 96-tap filter (XI, YI, XQ, and YQ together)

(opposite channel must be set to 000)

Table 13. Register 0x0DF9 Definition

Bit(s)

Description

Reserved

[6:4]

Y filter gain

110: −12 dB loss

111: −6 dB loss

000: 0 dB gain

001: 6 dB gain

010: 12 dB gain

Reserved

[2:0]

X filter gain

110: −12 dB loss

111: −6 dB loss

000: 0 dB gain

001: 6 dB gain

010: 12 dB gain

Table 14 and Table 15 show the coefficient tables in

are Q1.15 format (sign bit + 15 fractional bits).

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