 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AD9208 Datasheet(PDF) 95 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9208 Datasheet(HTML) 95 Page - Analog Devices |
|
|
95 / 137 page  AD9208 Data Sheet Rev. 0 | Page 94 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 0x000C Vendor ID LSB [7:0] Vendor ID LSB Vendor ID [7:0]. 0x56 R 0x000D Vendor ID MSB [7:0] Vendor ID MSB Vendor ID [15:8]. 0x04 R 0x000F Transfer [7:1] Reserved Reserved. 0x0 R 0 Chip transfer Self clearing chip transfer bit. This bit is used to update the DDC phase increment and phase offset registers when DDC phase update mode (Register 0x0300, Bit 7 ) = 1. This makes it possible to synchronously update the DDC mixer frequencies. This bit is also used to update the coefficients for the programmable filter (PFILT). 0x0 R/W 0 Do nothing. Bit is only cleared after transfer is complete. 1 Self clearing bit used to synchronize the transfer of data from master to slave registers. Clock/SYSREF/Chip PDWN Pin Control Registers 0x003F Chip PDWN pin (local) 7 Local chip PDWN pin disable Function is determined by Register 0x0040, Bits[7:6]. 0x0 R/W 0 Power-down pin (PDWN/STBY) enabled (default). 1 Power-down pin (PDWN/STBY) disabled/ignored. [6:0] Reserved Reserved. 0x0 R 0x0040 Chip Pin Control 1 [7:6] Global chip PDWN pin functionality External power-down pin functionality. Assertion of the external power-down pin (PDWN/STBY) has higher priority than the channel power mode control bits (Register 0x0002, Bits[1:0]). The PDWN/STBY pin is only used when Register 0x0040, Bits[7:6] = 00 or 01. 0x0 R/W 00 Power-down pin (default). Assertion of external power-down pin (PDWN/STBY) causes the chip to enter full power-down mode. 01 Standby pin. Assertion of external power-down pin (PDWN/STBY) causes the chip to enter standby mode. 10 Pin disabled. Power-down pin (PDWN/STBY) is ignored. [5:3] Chip FD_B/GPIO_B0 pin functionality Fast Detect B/GPIO B0 pin functionality. 0x7 R/W 000 Fast Detect B output. 001 JESD204B LMFC output. 110 Pin functionality determined by 0x0041[7:4] 111 Disabled. Configured as input with weak pull-down (default). [2:0] Chip FD_A/GPIO_A0 pin functionality Fast Detect A/GPIO A0 pin functionality. 0x7 R/W 000 Fast Detect A output. 001 JESD204B LMFC output. 110 Pin functionality determined by Register 0x0041, Bits[3:0] 111 Disabled. Configured as an input with weak pull-down (default). 0x0041 Chip Pin Control 2 [7:4] Chip FD_B/GPIO_B0 pin secondary functionality Fast Detect B/GPIO B0 pin secondary functionality (only used when Register 0x0040, Bits[5:3] = 110). 0x0 R/W 0000 Chip GPIO B0 input (NCO channel selection). 0001 Chip transfer input. 1000 Master next trigger output (MNTO). 1001 Slave next trigger input (SNTI). [3:0] Chip FD_A/GPIO_A0 pin secondary functionality Fast Detect A/GPIO B0 pin secondary functionality (only used when Register 0x0040, Bits[2:0] = 110). 0x0 R/W 0000 Chip GPIO A0 input (NCO channel selection). 0001 Chip transfer input. 1000 Master next trigger output (MNTO). 1001 Slave next trigger input (SNTI). |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
