AD9208 datasheet(49/137 Pages) AD

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AD9208

Data Sheet

Rev. 0 | Page 48 of 136

Only one NCO channel is active at a time and NCO channel

selection is controlled either by the CMOS GPIO pins or

through the register map.

Each NCO channel selector supports three different modes,

described as follows:



GPIO level control mode. In this mode, the GPIO pins

determine the exact NCO channel selected.



GPIO edge control mode. A low to high transition on a

single GPIO pin determines the exact NCO channel

selected. The internal channel selection counter is reset by

either SYSREF± or by the DDC soft reset.



selected is determined directly through the register map.

The following procedure must be followed to use GPIO level

control mode for NCO channel selection:

Configure one or more GPIO pins as NCO channel

selection inputs. The GPIO pins not configured as NCO

channel selection inputs are internally tied low.

To use GPIO_A0, write Bits[2:0] in Register 0x0040 to

0x6 and Bits[3:0] in Register 0x0041 to 0x0.

To use GPIO_B0, write Bits[5:3] in Register 0x0040 to

0x6 and Bits[7:4] in Register 0x0041 to 0x0.

To use GPIO_A1, write Bits[3:0] in Register 0x0042 to

0x0.

To use GPIO_B1, write Bits[7:4] in Register 0x0042 to

0x0.

Configure the NCO channel selector in GPIO level control

mode by setting Bits[7:4] in the NCO control registers

(Register 0x0314, Register 0x0334, Register 0x0354, and

desired GPIO pin order.

Select the desired NCO channel through the GPIO pins.

The following procedure must be followed to use GPIO edge

control mode for NCO channel selection:

Configure one or more GPIO pins as NCO channel

selection inputs.

To use GPIO_A0, write Bits[2:0] in Register 0x0040 to

0x6 and Bits[3:0] in Register 0x0041 to 0x0.

To use GPIO_B0, write Bits[5:3] in Register 0x0040 to

0x6 and Bits[7:4] in Register 0x0041 to 0x0.

To use GPIO_A1, write Bits[3:0] in Register 0x0042 to

0x0.

To use GPIO_B1, write Bits[7:4] in Register 0x0042 to

0x0.

Configure the NCO channel selector in GPIO edge control

mode by setting Bits[7:4] in the NCO control registers

(Register 0x0314, Register 0x0334, Register 0x0354, and

desired GPIO pin.

Configure the wrap point for the NCO channel selection

by setting Bits[3:0] in the NCO control registers

(Register 0x0314, Register 0x0334, Register 0x0354, and

to wrap at Channel 4 (for example, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4).

Transition the selected GPIO pin from low to high to

increment the NCO channel selection.

Figure 90 shows an example use case for coherent mode using

three NCO channels. In this example, NCO Channel 0 is actively

downconverting Bandwidth 0 (B0), while NCO Channel 1 and

Channel 2 are in standby mode and are tuned to Bandwidth 1

and Bandwidth 2 (B1 and B2), respectively.

fS/2

NCO CHANNEL 0

CARRIER FREQUENCY 0

(ACTIVE)

NCO CHANNEL 1

CARRIER FREQUENCY 1

(STANDBY)

NCO CHANNEL 2

CARRIER FREQUENCY 2

(STANDBY)

ACTIVE

DDC

Figure 90. NCO Coherent Mode with Three NCO Channels (B0 Selected)

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