AD9608 datasheet(36/41 Pages) AD

36 / 41 page

Data Sheet

AD9608

Rev. C | Page 35 of 40

Addr

(Hex)

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Default

Value

(Hex)

Comments

0x0B

Clock

divide

(global)

Open

Clock divide ratio

000 = divide by 1

001 = divide by 2

010 = divide by 3

011 = divide by 4

100 = divide by 5

101 = divide by 6

110 = divide by 7

111 = divide by 8

0x00

The divide

ratio is

value plus 1

0x0C

Enhance-

ment

control

(global)

Open

Chop mode

0 = disabled

1 = enabled

Open

0x00

Chop mode

enabled if

Bit 2 = 1

0x0D

Test

mode

(local)

User test mode control

00 = single pattern

mode

01 = alternate

continuous/repeat

pattern mode

10 = single once

pattern mode

11 = alternate once

pattern mode

ResetPN

longgen

Reset PN

short gen

Output test mode

0000 = off (default)

0001 = midscale short

0010 = positive FS

0011 = negative FS

0100 = alternating checkerboard

0101 = PN long sequence

0110 = PN short sequence

0111 = one/zero word toggle

1000 = user test mode

1111 = ramp output

0x00

When this

set, the test

data is

placed on

the output

pins in

place of

normal data

0x10

Customer

offset

adjust

(local)

Offset adjust in LSBs from +127 to −128

(twos complement format)

0x00

0x14

Output

mode

Output port logic

type (global)

00 = CMOS, 1.8 V

10 = LVDS, ANSI

11 = LVDS, reduced

range

Output

interleave

enable

(global)

Output

port disable

(local)

Open

(global)

Output

invert

(local)

Output format

00 = offset binary

01 = twos complement

10 = Gray code

0x00

Configures

the outputs

and the

format of

the data

0x15

Output

adjust

Open

CMOS 1.8 V DCO drive

strength

00 = 1×

01 = 2×

10 = 3×

11 = 4×

Open

CMOS 1.8 V data

drive strength

00 = 1×

01 = 2×

10 = 3×

11 = 4×

0x00

Determines

CMOS

output

drive

strength

properties

0x16

Clock

phase

control

(global)

Invert

DCO

clock

0 = not

inverted

1 =

inverted

Open

Input clock divider phase adjust

relative to the encode clock

000 = no delay

001 = 1 input clock cycle

010 = 2 input clock cycles

011 = 3 input clock cycles

100 = 4 input clock cycles

101 = 5 input clock cycles

110 = 6 input clock cycles

111 = 7 input clock cycles

0x00

Allows

selection of

clock delays

into the

input clock

divider

0x17

Output

delay

(global)

DCO

clock

delay

0 =

disabled

1 =

enabled

Open

Data delay

0 = disabled

1 = enabled

Open

Delay selection

000 = 0.56 ns

001 = 1.12 ns

010 = 1.68 ns

011 = 2.24 ns

100 = 2.80 ns

101 = 3.36 ns

110 = 3.92 ns

111 = 4.48 ns

0x00

This sets

the fine

output

delay of the

output

clock but

does not

change

internal

timing

0x18

VREF

select

(global)

Open

Internal VREF digital adjustment

000 = 1.0 V p-p

001 = 1.14 V p-p

010 = 1.33 V p-p

011 = 1.6 V p-p

100 = 2.0 V p-p

0x04

Select

and/or

adjust VREF

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