AD9608 datasheet(34/41 Pages) AD

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Data Sheet

AD9608

Rev. C | Page 33 of 40

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE

Each row in the memory map register table has eight bit locations.

The memory map is roughly divided into three sections: the chip

configuration registers (Address 0x00 to Address 0x02); the

channel index and transfer registers (Address 0x05 and

Address 0xFF) and the ADC functions registers, including setup,

control, and test (Address 0x08 to Address 0x102).

The memory map register table (see Table 18) lists the default

hexadecimal value for each hexadecimal address shown. The

column with the heading Bit 7 (MSB) is the start of the default

hexadecimal value given. For example, Address 0x05, the device

index register, has a hexadecimal default value of 0x03. This

means that in Address 0x05, Bits[7:2] = 0, and Bits[1:0] = 1.

This setting is the default channel index setting. The default

value results in both ADC channels receiving the next write

command. For more information about this function and others,

see the AN-877 Application Note, Interfacing to High Speed ADCs

via SPI. This application note details the functions controlled by

documented in the Memory Map Register Descriptions section.

Open Locations

All address and bit locations that are not included in Table 18

are not currently supported for this device. Unused bits of a

valid address location should be written with 0s. Writing to these

locations is required only when part of an address location is

open (for example, Address 0x05). If the entire address location

is open (for example, Address 0x13), this address location should

not be written to.

Default Values

After the AD9608 is reset, critical registers are loaded with

default values. The default values for the registers are given in

the memory map register table, Table 18.

Logic Levels

An explanation of logic level terminology follows:

•

“Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”

•

“Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

Channel-Specific Registers

Some channel setup functions can be programmed for each

channel individually. In these cases, channel address locations

are internally duplicated for each channel. These registers and

bits are designated in Table 18 as local. These local registers and

bits can be accessed by setting the appropriate Channel A or

Channel B bits in Register 0x05. If both bits are set, the

subsequent write affects the registers of both channels. In a read

cycle, only Channel A or Channel B should be set to read one of

the two registers. If both bits are set during an SPI read cycle,

the part returns the value for Channel A. Registers and bits

designated as global in Table 18 affect the entire part or the

channel features for which independent settings are not allowed

between channels.

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