AD9218 datasheet(11/29 Pages) AD

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AD9218

Rev. C | Page 10 of 28

TERMINOLOGY

Full-Scale Input Power

Analog Bandwidth

Expressed in dbm. Computed using the following equation:

The analog input frequency at which the spectral power of the

fundamental frequency (as determined by the FFT analysis) is

reduced by 3 dB.

⎟

⎠

⎞

⎜

⎝

⎛

−

001

log

INPUT

Scale

Full

Scale

Full

rms

Power

Aperture Delay

The delay between the 50% point of the rising edge of the

ENCODE command and the instant at which the analog input

is sampled.

Gain Error

Gain error is the difference between the measured and the ideal

full-scale input voltage range of the ADC.

Aperture Uncertainty (Jitter)

The sample-to-sample variation in aperture delay.

Harmonic Distortion, Second

The ratio of the rms signal amplitude to the rms value of the

second harmonic component, reported in dBc.

Crosstalk

Coupling onto one channel being driven by a low level signal

(–40 dBFS) when the adjacent interfering channel is driven by a

full-scale signal.

Harmonic Distortion, Third

The ratio of the rms signal amplitude to the rms value of the

third harmonic component, reported in dBc.

Differential Analog Input Resistance,

Differential Analog Input Capacitance,

Differential Analog Input Impedance

Integral Nonlinearity

The deviation of the transfer function from a reference line

measured in fractions of 1 LSB using a “best straight line”

determined by a least-square curve fit.

The real and complex impedances measured at each analog

input port. The resistance is measured statically and the

capacitance and differential input impedances are measured

with a network analyzer.

Minimum Conversion Rate

The encode rate at which the SNR of the lowest analog signal

frequency drops by no more than 3 dB below the guaranteed limit.

Differential Analog Input Voltage Range

The peak-to-peak differential voltage that must be applied to

the converter to generate a full-scale response. Peak differential

voltage is computed by observing the voltage on a single pin

and subtracting the voltage from the other pin, which is 180

degrees out of phase. Peak-to-peak differential is computed by

rotating the input phase 180 degrees and again taking the peak

measurement. The difference is then computed between both

peak measurements.

Maximum Conversion Rate

The encode rate at which parametric testing is performed.

Output Propagation Delay

The delay between the 50% level crossing of ENCODE A or

ENCODE B and the 50% level crossing of the respective

channel’s output data bit.

Noise (for Any Range Within the ADC)

Differential Nonlinearity

⎟

⎠

⎞

⎜

⎝

⎛

−

001

dBFS

dBc

dBm

NOISE

Signal

SNR

The deviation of any code width from an ideal 1 LSB step.

Effective Number of Bits (ENOB)

where Z is the input impedance, FS is the full scale of the device

for the frequency in question, SNR is the value for the particular

input level, and Signal is the signal level within the ADC

reported in dB below full scale. This value includes both

thermal and quantization noise.

The effective number of bits is calculated from the measured

SNR based on the equation

−

MEASURED

SNR

ENOB

Power Supply Rejection Ratio

ENCODE Pulse Width/Duty Cycle

The ratio of a change in input offset voltage to a change in

power supply voltage.

Pulse width high is the minimum amount of time that the

ENCODE pulse should be left in Logic 1 state to achieve rated

performance; pulse width low is the minimum time ENCODE

pulse should be left in low state. See timing implications of

changing tENCH in text. At a given clock rate, these specifications

define an acceptable ENCODE duty cycle.

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