AD9218 datasheet(19/29 Pages) AD

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AD9218

Rev. C | Page 18 of 28

THEORY OF OPERATION

ANALOG INPUT

The AD9218 ADC architecture is a bit-per-stage pipeline-type

converter utilizing switch capacitor techniques. These stages

determine the 7 MSBs and drive a 3-bit flash. Each stage

provides sufficient overlap and error correction, allowing

optimization of comparator accuracy. The input buffers are

differential, and both sets of inputs are internally biased. This

allows the most flexible use of ac-coupled or dc-coupled and

differential or single-ended input modes. The output staging

block aligns the data, carries out the error correction, and feeds

the data to output buffers. The set of output buffers are powered

from a separate supply, allowing adjustment of the output

voltage swing. There is no discernible difference in performance

between the two channels.

The analog input to the AD9218 is a differential buffer. For best

dynamic performance, impedance at A

AIN

and

should match.

Special care was taken in the design of the analog input section

of the AD9218 to prevent damage and data corruption when

the input is overdriven. The nominal input range is 1.024 V p-p.

Optimum performance is obtained when the part is driven

differentially where common-mode noise is minimized and

even-order harmonics are reduced. Figure 42 shows an example

of the AD9218 being driven differentially via a wideband RF

transformer for ac-coupled applications. As shown in Figure 43,

applications that require dc-coupled differential drives can be

accommodated using the AD8138 differential output op amp.

USING THE AD9218 ENCODE INPUT

AD9218

50Ω

ANALOG

SIGNAL

SOURCE

AIN

25Ω

0.1µF

1:1

Any high speed ADC is extremely sensitive to the quality of the

sampling clock provided by the user. A track-and-hold circuit is

essentially a mixer. Any noise, distortion, or timing jitter on the

clock is combined with the desired signal at the analog-to-

digital output. For that reason, considerable care has been taken

in the design of the ENCODE input of the AD9218, and the

user is advised to give commensurate thought to the clock

source. The ENCODE input is fully TTL/CMOS compatible.

Figure 42. Using a Wideband Transformer to Drive the AD9218

AD9218

50Ω

ANALOG

SIGNAL

SOURCE

AIN

10kΩ

5kΩ

AVDD

0.1µF

500Ω

525Ω

AD8138

VOCM

15pF

25Ω

DIGITAL OUTPUTS

The digital outputs are TTL/CMOS compatible for lower power

consumption. During power-down, the output buffers transition to

a high impedance state. A data format selection option supports

either twos complement (set high) or offset binary output (set

low) formats.

Figure 43. Using the AD8138 to Drive the AD9218

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