AD9430 datasheet(15/45 Pages) AD

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AD9430

Rev. E | Page 14 of 44

Pin Number

Mnemonic

Description

VIN–

Analog Input—Complement.

GND

Data Sync (Input)—Not Used in LVDS Mode. Tie to GND.

CLK+

Clock Input—True (LVPECL Levels).

CLK–

Clock Input—Complement (LVPECL Levels).

47, 54, 62, 75, 83

DRVDD

3.3 V Digital Output Supply (3.0 V to 3.6 V).

48, 53, 61, 67, 74, 82

DRGND1

Digital Output Ground.

D0–

D0 Complement Output Bit (LSB).

D0+

D0 True Output Bit (LSB).

D1–

D1 Complement Output Bit.

D1+

D1 True Output Bit.

D2–

D2 Complement Output Bit.

D2+

D2 True Output Bit.

D3–

D3 Complement Output Bit.

D3+

D3 True Output Bit.

D4–

D4 Complement Output Bit.

D4+

D4 True Output Bit.

DCO–

Data Clock Output—Complement.

DCO+

Data Clock Output—True.

D5–

D5 Complement Output Bit.

D5+

D5 True Output Bit.

D6–

D6 Complement Output Bit.

D6+

D6 True Output Bit.

D7–

D7 Complement Output Bit.

D7+

D7 True Output Bit.

D8–

D8 Complement Output Bit.

D8+

D8 True Output Bit.

D9–

D9 Complement Output Bit.

D9+

D9 True Output Bit.

D10–

D10 Complement Output Bit.

D10+

D10 True Output Bit.

D11–

D11 Complement Output Bit.

D11+

D11 True Output Bit.

OR–

Overrange Complement Output Bit.

OR+

Overrange True Output Bit.

1 AGND and DRGND should be tied together to a common ground plane.

2 Pin 33 can be tied to AVDD (as recommended) or left floating with no ill effects

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