AD9430 datasheet(27/45 Pages) AD

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AD9430

Rev. E | Page 26 of 44

ANALOG INPUT

The analog input to the AD9430 is a differential buffer. For

best dynamic performance, impedances at VIN+ and VIN–

should match. The analog input is optimized to provide

superior wideband performance and requires that the analog

inputs be driven differentially. SNR and SINAD performance

degrades significantly if the analog input is driven with a single-

ended signal.

A wideband transformer such as the Mini-Circuit® ADT1-1WT

can provide the differential analog inputs for applications that

require a single-ended-to-differential conversion. Both analog

inputs are self-biased by an on-chip resistor divider to a

nominal 2.8 V. (See the Equivalent Circuits section.)

Special care was taken in the design of the analog input section

of the AD9430 to prevent damage and corruption of data when

the input is overdriven. The nominal differential input range is

approximately 1.5 V p-p ~ (768 mV × 2). Note that the best

SNR performance is achieved with S5 = 0 (full scale = 1.5).

2.8V

VIN+

VIN–

768mV

S5 = GND

DIGITALOUT = ALL 1s

DIGITALOUT = ALL 0s

Figure 52. Differential Analog Input Range

2.8V

S5 = AVDD

768mV

VIN+

VIN– = 2.8V

2.8V

Figure 53. Single-Ended Analog Input Range

DS INPUTS (DS+, DS–)

In CMOS output mode, the data sync inputs (DS+, DS–) can be

used in applications that require a given sample to appear at a

specific output port (A or B) relative to a given external timing

signal. The DS inputs can also be used to synchronize two or

more ADCs in a system to maintain phasing between Port A

and Port B on separate ADCs (in effect, synchronizing multiple

DCO outputs). When DS+ is held high (DS– low), the ADC

data outputs and clock do not switch and are held static.

Synchronization is accomplished by the assertion (falling edge)

of DS+ within the timing constraints tSDS and tHDS, relative to a

clock rising edge. (On initial synchronization, tHDS is not

relevant.) If DS+ falls within the required setup time (tSDS)

before a given clock rising edge, N, the analog value at that

point in time is digitized and available at Port A, 14 cycles later

in interleaved mode.

The very next sample, N + 1, is sampled by the next rising clock

edge and available at Port B, 14 cycles after that clock edge. In

dual-parallel mode, Port A has a 15-cycle latency and Port B

has a 14-cycle latency, but data is available at the same time.

Driving the DS inputs of each ADC by the same sync signal

accomplishes this. An easy way to accomplish synchronization

is by a one-time sync at power-on reset. Note that when

running the AD9430 in LVDS mode, set DS+ to ground and

DS– to 3.3 V, as the DS inputs are relevant only in CMOS

output mode, simplifying the design for some applications as

well as affording superior SNR/SINAD performance at higher

encode/analog frequencies.

CMOS OUTPUTS

The off-chip drivers on the chip can be configured to provide

CMOS-compatible output levels via Pin S2. The CMOS digital

outputs (S2 = 0) are TTL/CMOS compatible for lower power

consumption. The outputs are biased from a separate supply

(DRVDD), allowing easy interface to external logic. The outputs

are CMOS devices that swing from ground to DRVDD (with no

dc load). It is recommended to minimize the capacitive load the

ADC drives by keeping the output traces short (<1 inch, for a

total CLOAD < 5 pF). When operating in CMOS mode, it is also

recommended to place low value (20 Ω) series damping

resistors on the data lines to reduce switching transient effects

on performance.

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