AD7889 datasheet(31/40 Pages) AD

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Data Sheet

AD7879/AD7889

Rev. D | Page 31 of 40

INTERRUPTS

The AD7879/AD7889 have a dual function interrupt output, INT,

as well as a pen-down interrupt, PENIRQ. The INT output can be

configured as a data available interrupt (DAV), as an out of limit

interrupt (INT), or as a GPIO interrupt.

DAV—Data Available Interrupt

The behavior of the interrupt output is controlled by Bit 13 in

Control Register 3. In default mode (Bit 13 = 0), INT operates

as a data available interrupt (DAV). When the AD7879/AD7889

finish a conversion or a conversion sequence, the interrupt is

asserted to let the host know that new ADC data is available in

the result registers.

While the ADC is idle or is converting, DAV is high. When the

ADC finishes converting and new data has been written to the

result registers, DAV goes low. Reading the result registers resets

DAV to a high condition. DAV is also reset if a new conversion

is started by the AD7879/AD7889 because the timer expired.

The host reads the result registers only when DAV is low. To ensure

correct operation of the DAV mode when using the SPI interface, it

is necessary to write 0x0000 to Register 0x81 after a set of

ADC

CONVERTING

SETUP

BY HOST

IDLE

NEW DATA

AVAILABLE

HOST READS

RESULTS

IDLE

tCONV

AD7879

STATUS

DAV

Figure 35. Operation of DAV Output

When the on-board timer is programmed to perform automatic

conversions, limited time is available to the host to read the

result registers before another sequence of conversions begins.

The DAV signal is reset high when the timer expires, and the

host should not access the result registers while DAV is high.

INT—Out of Limit Interrupt

The INT pin operates as an alarm or interrupt output when

Bit 13 in Control Register 3 (Address 0x03) is set to 1. The

output goes low if any one of the interrupt sources is asserted.

The results of high and low limit comparisons on the AUX,

VBAT, and TEMP channels are interrupt sources. An out of

limit comparison sets a status bit in the interrupt register. A

separate status bit for the high limit and the low limit on each

channel indicates which limit was exceeded. The interrupt

sources can be masked by setting the corresponding enable bit

in this register to 1. There is one enable bit per channel.

PENIRQ—Pen Interrupt

The pen interrupt request output (PENIRQ) goes low whenever

the screen is touched and the PENIRQ enable bit is set to 0

(Control Register 1, Bit 15). When PENIRQ enable is set to 1,

the pen interrupt request output is disabled.

The pen interrupt equivalent output circuitry is shown in Figure 36.

This digital logic output has an internal 50 kΩ pull-up resistor,

so it does not need an external pull-up. The PENIRQ output

idles high, and the PENIRQ circuitry is always enabled in

master mode (ADC mode = 11), except during conversions.

X+

TOUCH

SCREEN

Y+

50kΩ

Y–

X–

PENIRQ

ENABLE

PENIRQ

VCC

Figure 36. PENIRQ Output Equivalent Circuit

When the screen is touched, PENIRQ goes low. This generates

an interrupt request to the host. When the screen touch ends,

PENIRQ immediately goes high if the ADC is idle. If the ADC

is converting, PENIRQ goes high when the ADC becomes idle.

The PENIRQ operation for these two conditions is shown in

Figure 37.

SCREEN

PENIRQ

ADC

STATUS

TOUCHED

NOT

TOUCHED

NOT

TOUCHED

NOT

TOUCHED

NOT

TOUCHED

ADC IDLE

SCREEN

PENIRQ

ADC

STATUS

TOUCHED

ADC IDLE

ADC

CONVERTING

ADC IDLE

RELEASE NOT

DETECTED

PENIRQ

DETECTS

RELEASE

PENIRQ

DETECTS

RELEASE

PENIRQ

DETECTS

TOUCH

PENIRQ

DETECTS

TOUCH

Figure 37. PENIRQ Operation for ADC Idle and ADC Converting

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