AD6679 datasheet(49/82 Pages) AD

49 / 82 page

AD6679

Data Sheet

Rev. B | Page 48 of 81

For example, if the ADC sampling frequency (fS) is 500 MSPS

and the carrier frequency (fC) is 140.312 MHz, then



MHz

1149

500

312

140

mod

round

















FTW

NCO

This, in turn, converts to 0x47D in the 12-bit twos complement

representation for NCO_FTW. Calculate the actual carrier

frequency, fC_ACTUAL, based on the following equation:

MHz

140







ACTUAL

FTW

NCO

A 12-bit POW is available for each NCO to create a known

phase relationship between multiple AD6679 chips or

individual DDC channels inside one AD6679 chip.

The following procedure must be followed to update the FTW

and/or POW registers to ensure proper operation of the NCO:

Write to the FTW registers for all the DDCs.

Write to the POW registers for all the DDCs.

Synchronize the NCOs either through the DDC NCO soft

reset bit (Register 0x300, Bit 4), accessible through the SPI

or through the assertion of the SYNC± pin.

It is important to note that the NCOs must be synchronized

either through the SPI or through the SYNC± pin after all

writes to the FTW or POW registers are complete. This

synchronization is necessary to ensure the proper operation

of the NCO.

NCO Synchronization

Each NCO contains a separate phase accumulator word (PAW)

that determines the instantaneous phase of the NCO. The initial

reset value of each PAW is determined by the POW. The phase

increment value of each PAW is determined by the FTW. See

the Setting Up the NCO FTW and POW section for more

information.

Use the following two methods to synchronize multiple PAWs

within the chip:



Using the SPI. Use the DDC NCO soft reset bit in the DDC

synchronization control register (Register 0x300, Bit 4) to

reset all the PAWs in the chip. This is accomplished by

setting the DDC NCO soft reset bit high and then setting

this bit low. Note that this method synchronizes DDC

channels within the same AD6679 chip only.



Using the SYNC± pins. When the SYNC± pins are

enabled in the SYNC± control registers (Register 0x120

and Register 0x121) and the DDC synchronization is

enabled in the DDC synchronization control register

(Register 0x300, Bits[1:0]), any subsequent SYNC± event

resets all the PAWs in the chip. Note that this method

synchronizes DDC channels within the same AD6679 chip

or DDC channels within separate AD6679 chips.

Mixer

The NCO is accompanied by a mixer. Its operation is similar to

an analog quadrature mixer. It performs the downconversion of

input signals (real or complex) by using the NCO frequency as a

local oscillator. For real input signals, this mixer performs a real

mixer operation (with two multipliers). For complex input

signals, the mixer performs a complex mixer operation (with

four multipliers and two adders). The mixer adjusts its

operation based on the input signal (real or complex) provided

to each individual channel. The selection of real or complex

inputs can be controlled individually for each DDC block using

Bit 7 of the DDC control registers (Register 0x310, Register 0x330,

AD6679 Datasheet(PDF) 49 Page - Analog Devices

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