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AD9863

Data Sheet

Rev. B | Page 20 of 40

The degradation in SNR at a given full-scale input frequency

(fINPUT), due to aperture jitter (tA), can be calculated with the

following equation:

SNR degradation = 20 log [(½)πFINtA)]

In the equation, the rms aperture jitter, tA, represents the root-

sum-square of all jitter sources, which includes the clock input,

analog input signal, and ADC aperture jitter specification.

Undersampling applications are particularly sensitive to jitter.

The clock input is a digital signal that must be treated as an

analog signal with logic level threshold voltages, especially in

cases where aperture jitter may affect the dynamic range of the

AD9863. Power supplies for clock drivers must be separated

from the ADC output driver supplies to avoid modulating the

clock signal with digital noise. Low jitter crystal-controlled

oscillators make the best clock sources. If the clock is generated

from another type of source (by gating, dividing, or other meth-

ods), it must be retimed by the original clock at the last step.

Power Dissipation and Standby Mode

The power dissipation of the AD9863 Rx path is proportional to

its sampling rate. The Rx path portion of the digital (DRVDD)

power dissipation is determined primarily by the strength of the

digital drivers and the load on each output bit. The digital drive

current can be calculated by

IDRVDD = VDRVDD × CLOAD × fCLOCK × N

where N is the number of bits changing and CLOAD is the average

load on the digital pins that changed.

The analog circuitry is optimally biased so that each speed

grade provides excellent performance while affording reduced

power consumption. Each speed grade dissipates a baseline

power at low sample rates, which increases with clock fre-

quency. The baseline power dissipation for either speed grade

can be reduced by asserting the ADC_LO_PWR pin, which

reduces internal ADC bias currents by half, in some cases

resulting in degraded performance.

To further reduce power consumption of the ADC, the

ADC_LO_PWR pin can be combined with a serial programmable

power mode reduces power consumption by a fourth of the normal

power consumption. The ultralow power mode can be used at

slower sampling frequencies or if reduced performance is

acceptable. To configure the ultralow power mode, assert the

ADC_LO_PWR pin during power-up and write the following

(MSB) 0000 1100

(MSB) 0111 0000

Figure 49 shows the typical analog power dissipation

(ADC_AVDD = 3.3 V) for the ADC vs. sampling rate for the

normal power, low power, and ultralow power modes.

Either of the ADCs in the AD9863 Rx path can be placed in

standby mode independently by writing to the appropriate SPI

standby power is achieved when both channels are placed in full

power-down mode using the appropriate SPI register bits in

internal references are powered down. When either or both of the

channel paths are enabled after a power-down, the wake-up time is

directly related to the recharging of the REFT and REFB

decoupling capacitors and the duration of the power-down.

Typically, it takes approximately 5 ms to restore full operation with

fully discharged 0.1 µF and 10 µF decoupling capacitors on REFT

and REFB.

100

120

Rx PATH SAMPLING RATE (MHz)

ULTRALOW POWER

LOW POWER

NORMAL

Figure 49. Typical Rx Path Analog Supply Current vs. Sample Rate,

VDD = 3.3 V for Normal, Low, and Ultralow Power Modes

Tx PATH BLOCK

The AD9863 transmit (Tx) path includes dual interpolating 12-bit

current output DACs that can be operated independently or can

be coupled to form a complex spectrum in an image reject transmit

architecture. Each channel includes two FIR filters, making the

AD9863 capable of 1×, 2×, or 4× interpolation. High speed input

and output data rates can be achieved within the limitations listed

in Table 9.

Table 9. AD9863 Tx Path Maximum Data Rate

Interpolation

Rate

24-Bit Interface

Mode

Input Data

Rate per

Channel

(MSPS)

DAC

Sampling

Rate

(MSPS)

1×

FD, HD12, Clone

HD24

160

2×

FD, HD12, Clone

160

HD24

160

4×

FD, HD12, Clone

200

HD24

200

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