AD9869BCPZ datasheet(33/37 Pages) AD

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AD9869

Rev. A | Page 32 of 36

Because the CPGA processes signals in the continuous time

domain, its performance vs. bias setting remains mostly

independent of the sample rate. Table 25 shows how the typical

current consumption seen at AVDD varies as a function of

their default settings of 0. Only four of the possible settings result

in any reduction in current consumption relative to the default

setting. Reducing the bias level typically results in degradation

in the THD vs. frequency performance as shown in Figure 35.

This is due to a reduction of the amplifier’s unity gain bandwidth,

while the SNR performance remains relatively unaffected.

Table 25. Analog Supply Current vs. CPGA Bias Settings at

fADC = 65 MSPS

Bit 7

Bit 6

Bit 5

∆mA

−27

−42

−51

−55

+27

+69

+27

CPGA BIAS SETTING-BITS (7:5)

000

100

010

011

001

65.0

40.0

–20

–70

–65

–60

–55

–50

–45

–40

–35

–30

–25

42.5

45.0

47.5

50.0

52.5

55.0

57.5

60.0

62.5

SNR_RxPGA = 0dB

SNR_RxPGA = 36dB

THD_RxPGA = 0dB

THD_RxPGA = 36dB

Figure 35. THD vs. fIN Performance and CPGA Bias Settings (000, 001, 010, 100

with RxPGA = 0 and +36 dB, AIN = −1 dBFS, LPF set to 26 MHz, fADC = 50 MSPS)

The SPGA is implemented as a switched capacitor amplifier,

therefore, its performance vs. bias level is mostly dependent on

the sample rate. Figure 36 shows how the typical current consump-

tion seen at AVDD varies as a function of Register 0x13, Bits[4:3]

and sample rate, while the remaining bits are maintained at the

default setting of 0. Figure 37 shows how the SNR and THD

performance is affected for a 10 MHz sine wave input as the

ADC sample rate is swept from 20 MHz to 80 MHz. The SNR

and THD performance remains relatively stable, suggesting that

the SPGA bias can often be reduced from its default setting

without impacting the device’s overall performance.

ADC SAMPLE RATE (MSPS)

210

170

175

180

185

190

195

200

205

Figure 36. AVDD Current vs. SPGA Bias Setting and Sample Rate

SAMPLE RATE (MSPS)

–54

–74

–72

–70

–68

–66

–64

–62

–60

–58

–56

SNR-00

SNR-01

SNR-10

SNR-11

THD-00

THD-01

THD-10

THD-11

Figure 37. SNR and THD Performance vs. fADC and SPGA Bias Setting with

RxPGA = 0 dB, fIN = 10 MHz, LPF set to 26 MHz, AIN = −1 dBFS

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