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AD9869BCPZ Datasheet(PDF) 13 Page - Analog Devices

Part # AD9869BCPZ
Description  Broadband Modem Mixed-Signal Front End
PDF  37 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9869BCPZ Datasheet(HTML) 13 Page - Analog Devices

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AD9869
Rev. A | Page 12 of 36
SERIAL PORT
Table 10. SPI Register Mapping
Power-Up Default Value
MODE = 0
(Half-Duplex)
MODE = 1
(Full-Duplex)
Address
(Hex)
Bit1
Description
Width
CONFIG = 0
CONFIG = 1
CONFIG = 0
Comments
SPI PORT CONFIGURATION AND SOFTWARE RESET
0x00
7
4-Wire SPI
1
0
0
0
6
SPI LSB First
1
0
0
0
5
Software Reset
1
0
0
0
Default SPI configuration is 3-wire,
MSB first.
POWER CONTROL REGISTERS (Via PWRDWN Pin)
0x01
7
CLK Synthesizer
1
0
0
0
6
TxDAC/IAMP
1
0
0
0
5
Tx Digital
1
0
0
0
4
REF
1
0
0
0
3
ADC CML
1
0
0
0
2
ADC
1
0
0
0
1
PGA Bias
1
0
0
0
0
RxPGA
1
0
0
0
PWRDWN = 0.
Default setting is for all blocks powered on.
0x02
7
CLK Synthesizer
1
0
0
0
6
TxDAC/IAMP
1
1
1
1
5
Tx Digital
1
1
1
1
4
REF
1
1
1
1
3
ADC CML
1
1
1
1
2
ADC
1
1
1
1
1
PGA Bias
1
1
1
1
0
RxPGA
1
1
1
1
PWRDWN = 1.
Default setting is for all functional blocks
powered down except PLL.
HALF-DUPLEX POWER CONTROL
0x03
7:3
Tx OFF Delay
5
0xFF
0xFF
N/A
2
Rx_TXEN
1
0xFF
0xFF
N/A
1
Tx PWRDN
1
0xFF
0xFF
N/A
0
Rx PWRDN
1
0xFF
0xFF
N/A
Default setting is for TXEN input to
control power-on/power-off of Tx/Rx
path. Tx driver delayed by 31 1/fDATA clock
cycles.
PLL CLOCK MULTIPLIER/SYNTHESIZER CONTROL
0x04
4
fADC from PLL
1
0
0
0
3:2
PLL Divide-N
2
00
00
00
1:0
PLL Multiplier-M
2
01
10
01
0x05
2
OSCIN to RXCLK
1
0
0
0
1
Invert RXCLK
1
0
0
0
0
Disable RXCLK
1
0
0
0
Full-duplex RXCLK normally at nibble rate.
0x06
7:6
CLKOUT2 Divide
2
01
01
01
5
CLKOUT2 Invert
1
0
0
0
4
CLKOUT2 Disable
1
0
0
0
3:2
CLKOUT1 Divide
2
01
01
01
1
CLKOUT1 Invert
1
0
0
0
0
CLKOUT1 Disable
1
0
0
0
Default setting is CLKOUT2 and
CLKOUT1 enabled with divide-by-2.
Rx PATH CONTROL
0x07
5
Initiate Offset Cal.
1
0
0
0
4
Rx Low Power
1
0
1
0
0
Enable Rx LPF
1
1
1
1
Default setting has LPF on.
Rx path at nominal power bias setting for
CONFIG = 0 and low power for CONFIG = 1.
0x08
7:0
Rx Filter Target
Cutoff Frequency
8
0x80
0x61
0x80
Refer to the Low-Pass Filter section.



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