AD9869BCPZ datasheet(28/37 Pages) AD

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AD9869

Rev. A | Page 27 of 36

Table 20 shows the SPI registers pertaining to the ADC.

Table 20. SPI Registers for Rx ADC

Address (Hex)

Bit

Description

0x04

ADC clock from PLL.

0x07

ADC low power mode.

0x13

2:0

ADC power bias adjust.

AGC TIMING CONSIDERATIONS

When implementing a digital AGC timing loop, it is important

to consider the Rx path latency and settling time of the Rx path

in response to a change in gain setting. While the RxPGA

settling time may also show a slight dependency on the LPF

cutoff frequency, the ADC pipeline delay, along with the ADIO

bus interface, presents a more significant delay. The amount of

delay or latency is dependent on whether a half-duplex or full-

duplex is selected. An impulse response at the RxPGA input can

be observed after 10.0 ADC clock cycles (1/fADC) in the case of a

half-duplex interface, and 10.5 ADC clock cycles in the case of a

full-duplex interface. This latency, along with the RxPGA settling

time, should be considered to ensure stability of the AGC loop.

AD9869BCPZ Datasheet(PDF) 28 Page - Analog Devices