AD9869BCPZ datasheet(27/37 Pages) AD

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AD9869

Rev. A | Page 26 of 36

TARGET-DECIMAL EQUIVALENT

128

224

192

112

176

144 160

208

50MSPS CALCULATED

80MSPS CALCULATED

50MSPS MEASURED

80MSPS MEASURED

Figure 29. Measured and Calculated f−3 dB vs. Target Value for

fADC = 50 MSPS and 80 MSPS

The following scaling factor can be applied to the previous

formula to compensate for the RxPGA gain setting on f−3 dB:

Scale Factor = 1 − (RxPGA in dB)/382

(6)

This scaling factor reduces the calculated f−3 dB as the RxPGA

increases. Applications that need to maintain a minimum cutoff

frequency, f−3 dB_MIN, for all RxPGA gain settings should first

determine the scaling factor for the highest RxPGA gain setting

to be used. Next, the f−3 dB_MIN should be divided by this scale

factor to normalize to the 0 dB RxPGA gain setting, f−3 dB_0 dB.

Equation 5 can then be used to calculate the target value.

The LPF frequency response shows a slight sensitivity to

temperature, as shown in Figure 30. Applications sensitive to

temperature drift can recalibrate the LPF by rewriting the target

value to Register 0x08.

TARGET-DECIMAL EQUIVALENT

128

240

192

176

112

144

160

208

fOUT ACTUAL 80MHz AND –40°C

224

fOUT ACTUAL 80MHz AND +25°C

fOUT ACTUAL 80MHz AND +85°C

Figure 30. f−3 dB Temperature Drift for fADC = 80 MSPS and RxPGA = 0 dB

ANALOG-TO-DIGITAL CONVERTER (ADC)

The AD9869 features a 12-bit analog-to-digital converter

(ADC) capable of up to 80 MSPS. As shown in Figure 24, the

ADC is driven by the SPGA stage, which performs both the

sample-and-hold and the fine gain adjust functions. A buffer

amplifier (not shown) isolates the last CPGA gain stage from

the dynamic load presented by the SPGA stage. The full-scale

input span of the ADC is 2 V p-p, and depending on the PGA

gain setting, the full-scale input span into the SPGA is adjustable

from 1 V to 2 V in 1 dB increments.

A pipelined, multistage ADC architecture is used to achieve high

sample rates while consuming low power. The ADC distributes the

conversion over several smaller ADC subblocks, refining the

conversion with progressively higher accuracy as it passes the

results from stage to stage on each clock edge. The ADC typically

performs best when driven internally by a 50% duty cycle clock.

The ADC power consumption can be reduced by 25 mA with

minimal effect on its performance by setting Bit 4 of Register 0x07.

Alternative power bias settings are also available via Register 0x13,

as discussed in the Power Control and Dissipation section.

Lastly, the ADC can be completely powered down for half-duplex

operation, further reducing the peak power consumption of the

AD9869.

The ADC has an internal voltage reference and reference amplifier

as shown in Figure 31. The internal band gap reference generates

a stable 1 V reference level that is converted to a differential 1 V

reference centered about midsupply (AVDD/2). The outputs of

the differential reference amplifier are available at the REFT and

REFB pins and must be properly decoupled for optimum perform-

ance. The REFT and REFB pins are conveniently situated at

the corners of the LFCSP package such that C1 (0603 type)

can be placed directly across its pins. C3 and C4 can be placed

underneath C1, and C2 (10 μF tantalum) can be placed furthest

from the package.

1.0V

ADCs

REFT

REFB

0.1µF

10µF

0.1µF

TOP

VIEW

Figure 31. ADC Reference and Decoupling

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