AD9869

Rev. A | Page 2 of 36

TABLE OF CONTENTS

Features .............................................................................................. 1

 

Applications....................................................................................... 1

 

Functional Block Diagram .............................................................. 1

 

General Description ......................................................................... 1

 

Revision History ............................................................................... 2

 

Specifications..................................................................................... 3

 

Tx Path Specifications.................................................................. 3

 

Rx Path Specifications.................................................................. 4

 

Power Supply Specifications........................................................ 6

 

Digital Specifications ................................................................... 7

 

Serial Port Timing Specifications ............................................... 7

 

Half-Duplex Data Interface (ADIO Port) Timing

Specifications ................................................................................ 8

 

Full-Duplex Data Interface (Tx and Rx Port) Timing

Specifications ................................................................................ 8

 

Absolute Maximum Ratings............................................................ 9

 

Thermal Characteristics .............................................................. 9

 

Explanation of Test Levels ........................................................... 9

 

ESD Caution.................................................................................. 9

 

Pin Configuration and Function Descriptions........................... 10

 

Serial Port ........................................................................................ 12

 

Register Map Description.......................................................... 14

 

Serial Port Interface (SPI).......................................................... 14

 

Digital Interface .............................................................................. 16

 

Half-Duplex Mode ..................................................................... 16

 

Full-Duplex Mode ...................................................................... 17

 

RxPGA Control .......................................................................... 19

 

TxPGA Control .......................................................................... 20

 

Transmit Path.................................................................................. 21

 

Digital Interpolation Filters ...................................................... 21

 

TxDAC and IAMP Architecture .............................................. 22

 

Tx Programmable Gain Control .............................................. 23

 

TxDAC Output Operation........................................................ 23

 

IAMP Current-Mode Operation.............................................. 23

 

Receive Path .................................................................................... 24

 

Rx Programmable Gain Amplifier........................................... 24

 

Low-Pass Filter............................................................................ 25

 

Analog-to-Digital Converter (ADC)....................................... 26

 

AGC Timing Considerations.................................................... 27

 

Clock Synthesizer ........................................................................... 28

 

Power Control and Dissipation .................................................... 30

 

Power-Down ............................................................................... 30

 

Half-Duplex Power Savings ...................................................... 30

 

Power Reduction Options ......................................................... 31

 

Power Dissipation....................................................................... 33

 

Mode Select upon Power-Up and Reset.................................. 33

 

Analog and Digital Loopback Test Modes.............................. 34

 

Outline Dimensions ....................................................................... 35

 

Ordering Guide .......................................................................... 35

 

REVISION HISTORY

8/11—Rev. 0 to Rev. A

Changes to Figure 1.......................................................................... 1

Deleted Lead Temperature Parameter, Table 8 ............................. 9

Changes to Figure 2 and Table 9................................................... 10

Changes to Figure 9........................................................................ 16

Changes to Figure 10, Figure 11, and Figure 12 ......................... 17

Changes to Figure 13...................................................................... 18

Changes to Figure 18...................................................................... 21

5/07—Revision 0: Initial Version