AD9869BCPZ datasheet(19/37 Pages) AD

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AD9869

Rev. A | Page 18 of 36

The Rx[5:0] port operates in the following manner with the SPI

Two consecutive nibbles of the Rx data are multiplexed

together to form a 12-bit data-word in twos complement

format.

The Rx data is valid on the rising edge of RXCLK, as

illustrated in the timing diagram shown in Figure 13.

The RXSYNC signal is used to indicate which word belongs

to which nibble. While RXSYNC is low, the first nibble of

every word is transmitted as the most significant nibble.

The second nibble of that same word is transmitted on the

following RXSYNC high level as the least significant nibble.

RXCLK

RXSYNC

Rx[5:0]

Rx0LSB

Rx1MSB

Rx1LSB

Rx2MSB

Rx2LSB

Rx3MSB

tDV

tDH

Figure 13. Full-Duplex Rx Port Timing

To add flexibility to the full-duplex digital interface port, several

programming options are available in the SPI registers. These

options are listed in Table 14. The timing for the Tx[5:0] and/or

Rx[5:0] ports can be independently changed by selecting either

the rising or falling clock edge as the sampling/validating edge

of the clock. Inverting RXCLK (via Bit 1 of Register 0x05) affects

both the Rx and Tx interface because they both use RXCLK.

Table 14. SPI Registers for Full-Duplex Interface

Address (Hex)

Bit

Description

0x05

OSCIN to RXCLK.

Invert RXCLK.

Disable RXCLK.

0x0B

Rx gain on Tx port.

0x0C

Invert TXSYNC.

Tx 5/5 nibble.

LS nibble first.

TXCLK negative edge.

Twos complement.

0x0D

Rx port three-state.

Invert RXSYNC.

Rx 5/5 nibble.

LS nibble first.

RXCLK negative edge.

Twos complement.

0x0E

Low digital drive strength.

The default Tx and Rx data input formats are twos complement,

but can be changed to straight binary. The default TXSYNC and

RXSYNC settings can be changed such that the first nibble of the

word appears while either TXSYNC, RXSYNC, or both are high.

In addition, the least significant nibble can be selected as the

first nibble of the word (least significant nibble first). The

output driver strength can also be reduced for lower data rate

applications.

For the AD9869, the most significant nibble defaults to 6 bits,

and the least significant nibble defaults to 4 bits. This can be

changed so that the least significant nibble and most significant

nibble have 5 bits each. To accomplish this, set the 5/5 nibble bit

(Bit 3 in Register 0x0C and Bit 3 in Register 0x0D), and use the

Tx[5:1] and Rx[5:1] data pins.

Figure 14 shows a possible digital interface between an ASIC

and the AD9869. The AD9869 serves as the master generating

the required clocks for the ASIC. This interface requires that the

ASIC reserve 16 pins for the interface, assuming a 6-bit nibble

width and the use of the Tx port for RxPGA gain control. Note

that the ASIC pin allocation can be reduced by 3 if a 5-bit nibble

width is used and the gain (or gain strobe) of the RxPGA is

controlled via the SPI port.

Tx DIGITAL

FILTER

10/12

AD9868/AD9869

FROM

RxADC

10/12

RXSYNC

TXSYNC

TX_SYNC

RXCLK

CLKOUT1

CLKOUT2

CLKIN

DIGITAL ASIC

OSCIN

FROM

CRYSTAL

OR MASTER CLK

GAIN

OPTIONAL

Tx DATA[5:0]

Rx DATA[5:0]

Rx[5:0]

RX_SYNC

Tx[5:0]

RxPGA

Figure 14. Example of a Full-Duplex Digital Interface

with Optional RxPGA Gain Control via Tx[5:0]

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