AD9869BCPZ datasheet(29/37 Pages) AD

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AD9869

Rev. A | Page 28 of 36

CLOCK SYNTHESIZER

The AD9869 generates all its internal sampling clocks, as well as

two user-programmable clock outputs appearing at CLKOUT1

and CLKOUT2, from a single reference source (see Figure 32).

The reference source can either be a fundamental frequency or

an overtone quartz crystal connected between OSCIN and

XTAL, with the parallel resonant load components specified by

the crystal manufacturer. It can also be a TTL-level clock

applied to OSCIN with XTAL left unconnected.

÷2N

XTAL

÷2L

÷2R

2M CLK

MULTIPLIER

XTAL

OSCIN

CLKOUT2

CLKOUT1

TO ADC

TO TxDAC

÷F/2

RXCLK

(FULL-DUPLEX ONLY)

Figure 32. Clock Oscillator and Synthesizer

Special consideration should be given to the design of crystal

oscillators using the AD9869 internal CMOS inverter. This is

especially true when designing third overtone oscillators where

crystal power dissipation and negative resistance upon start-up

are a few of the issues to consider. For this reason, a 40 MHz or

lower fundamental crystal is preferred with the AD9869.

The CMOS inverter device characteristics are listed in Table 21. It

is recommended to consult with the selected crystal manufacturer

to ensure that a robust design can be realized with the selected

crystal and AD9869 CMOS inverter.

Table 21. CMOS Inverter Device Characteristics

Parameter

Nominal

Value

Tolerance %

Description

1.2 MΩ

±25

Feedback resistor.

17 mA/V

±20

At midsupply.

ZOUT

1.6 kΩ

±50

At midsupply.

CIN

2.5 pF

±25

Parasitic capacitance.

COUT

2.0 pF

±25

Parasitic capacitance.

The data rate, fDATA, for the Tx and Rx data paths must always be

equal. Therefore, the ADC sample rate, fADC, is always equal to

fDATA, while the TxDAC update rate is a factor of 1, 2, or 4 of

fDATA, depending on the selected interpolation factor. The data

rate refers to the word rate and should not be confused with the

nibble rate in full-duplex interface.

The 2M CLK multiplier contains a PLL (with integrated loop

filter) and a VCO capable of generating an output frequency

that is a multiple of 1, 2, 4, or 8 of its input reference frequency,

fOSCIN, appearing at OSCIN. The input frequency range of fOSCIN

is between 20 MHz and 80 MHz, and the VCO can operate over

an 80 MHz to 200 MHz span. For the best phase noise/jitter

characteristics, it is advisable to operate the VCO with a

frequency between 100 MHz and 200 MHz. The VCO output

drives the TxDAC directly such that its update rate, fDAC, is

related to fOSCIN by the following equation:

fDAC = 2M × fOSCIN

(7)

where M = 0, 1, 2, or 3.

M is the PLL multiplication factor set in Register 0x04. The

value of M is determined by the Tx path’s word rate, fDATA, and

digital interpolation factor, F, as shown in the following

equation:

M = log2 (F × fDATA/fOSCIN)

(8)

Note that if the reference frequency appearing at OSCIN is

chosen to be equal to the Tx path and Rx path word rates, M is

equal to log2(F). Also note that the RXCLK frequency for full-

duplex mode (MODE = 1) is a function of the 2M CLK

multiplier setting, as well as the interpolation factor, F. Full-

duplex mode requires that RXCLK be equal to 2 × fDATA because

data is transferred in nibbles.

The clock source for the ADC can be selected in Register 0x04

as a buffered version of the reference frequency appearing at

OSCIN (default setting) or a divided version of the VCO

output, fDAC. The first option is the default setting and most

desirable if fOSCIN is equal to fADC. This option typically results in

the best jitter/phase noise performance for the ADC sampling

clock. The second option is suitable in cases where fOSCIN is a

factor of 2 or 4 less than the fADC. In this case, the divider ratio,

N, is chosen such that the divided down VCO output is equal to

the ADC sample rate, as shown in the following equation:

fADC = fDAC/2N

(9)

where N = 0, 1, or 2.

The CLK synthesizer also has two clock outputs appearing at

CLKOUT1 and CLKOUT2. They are programmable via

voltage levels appearing at these outputs are relative to DRVDD

and remain active during a hardware or software reset. Table 22

shows the SPI registers pertaining to the CLK synthesizer.

Table 22. SPI Registers for CLK Synthesizer

Address (Hex)

Bit

Description

0x04

ADC CLK from PLL.

3:2

PLL divide factor (N).

1:0

PLL multiplication factor (M).

0x06

7:6

CLKOUT2 divide number.

CLKOUT2 invert.

CLKOUT2 disable.

3:2

CLKOUT1 divide number.

CLKOUT1 invert.

CLKOUT1 disable.

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