ADF9010 datasheet(23/29 Pages) AD

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ADF9010

Rev. 0 | Page 22 of 28

Rx Calibration Divider

Bit RC6 to Bit RC1 program a 6-bit divider, which outputs

a divided REFIN signal to assist calibration of the cutoff

frequency, fC, of the Rx filters. The calibration circuit uses

this divideddown PLL reference frequency to ensure an

accurate cutoff frequency in the Rx filter. The divider value

should be chosen to ensure that the frequency of the divided

down signal is exactly 2 MHz, that is, if a 32 MHz crystal is

used as the PLL REFIN frequency, then a value of 16 should

be programmed to the counter to ensure accurate calibration.

High-Pass Filter Boost Timeout Counter

In most applications of the ADF9010, a high-pass filter is placed

between the demodulator outputs and the ADF9010 Rx inputs.

The capacitors used in these filters may require a long charge

up time, and to address this, a filter boost function exists that

charges up the capacitor to ~1.6 V. The duration for this boost

is set by the product of the period of the Rx calibration signal,

(REFIN divided by the Rx calibration divider) and the 6-bit value

programmed to these registers. This value can be as large as 63.

Programming a value of 000000 leads to the calibration time

being manually set by the HPF boost in the Rx latch. It becomes

necessary in such cases to program this bit to 0 for normal Rx

operation.

LO LATCH

Program the LO latch with (C2, C1) = (1, 0). Figure 25 shows

the input data format for programming the LO latch.

Prescaler

Bit P2 and Bit P1 in the LO latch set the prescaler values.

CP Gain

Setting G1 to 0 chooses the programmed charge pump current

setting from the control latch. Setting this bit to 1 chooses the

maximum possible setting.

N Div Mux

Setting M1 to 0 feeds the VCO signals back to the N divider.

Setting this bit to 1 allows the mux signal to be fed back instead.

B Counter Latch

Bit B13 to Bit B1 program the B counter. The divide range is

3 (00 … 0011) to 8191 (11 … 111).

A Counter Latch

Bit A5 to Bit A1 program the 5-bit A counter. The divide range

is 0 (00000) to 31 (11111).

Rx LATCH

Program the Rx latch with (C2, C1) = (1, 1). Figure 26 shows

the input data format for programming the LO latch.

High-Pass Filter Boost

This function is enabled by setting the HP bit to 1. A 0 disables

this function. This is used to reduce settling time on the high-

pass filter from the Rx demodulator. This is usually used in

conjunction with the high-pass filter boost counter (See the

Rx Calibration Latch section).

Rx Filter Bandwidth

The Rx filter bandwidth is programmable and is controlled by

Bit BW2 and Bit BW1. See the truth table in Figure 26.

Rx Filter Gain Steps

Bit G3 to Bit G1 set the gain of the Rx filters. The gain can

vary from 3 dB to 24 dB in 3 dB steps. See the truth table in

Figure 26.

INITIALIZATION

The correct initialization sequence for the ADF9010 is as follows:

Power-down all blocks: Tx, Rx, PLL, and VCO. Set the Tx

output power off control latch to (1, 1). Set the LO phase

select off (P1, P2, P3) in Tx latch to (1, 1, 1).

Program the R1 latch with the desired R counter and

Tx values.

Program R5 with Rx calibration data for frequency

calibration and high-pass filter boost.

Program R0 to power up all LO and Tx/Rx blocks.

Program R2 to encode correct LO frequency.

Program R3 to power up Rx filter.

INTERFACING

The ADF9010 has a simple SPI®-compatible interface for

writing to the device. SCLK, SDATA, and SLE control the data

transfer. See Figure 2 for the timing diagram.

The maximum allowable serial clock rate is 20 MHz. This

means that the maximum update rate possible for the device

is 833 kHz or one update every 1.2 μs. This is certainly more

than adequate for systems that have typical lock times in

hundreds of microseconds.

ADF9010 Datasheet(PDF) 23 Page - Analog Devices

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