AR0141CS datasheet(16/48 Pages) ONSEMI

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AR0141CS

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SENSOR PLL

VCO

Figure 18. PLL Dividers Affecting VCO Frequency

pre_pll_clk_div

2(1−64)

pll_multiplier

58(32−384)

FVC0

EXTCLK

(6−50 MHz)

The sensor contains a phase−locked loop (PLL) that is

used for timing generation and control. The required VCO

clock frequency is attained through the use of a pre−PLL

clock divider followed by a multiplier. The PLL multiplier

should be an even integer. If an odd integer (M) is

programmed, the PLL will default to the lower (M−1) value

to maintain an even multiplier value. The multiplier is

followed by a set of dividers used to generate the output

clocks required for the sensor array, the pixel analog and

digital readout paths, and the output parallel and serial

interfaces.

Parallel PLL Configuration

Figure 19. PLL for the Parallel Interface

EXTCLK

(6−50 MHz)

CLK_OP

(Max 74.25 Mp/s)

FVC0

pre_pll_clk_div

2(1−64)

pll_multiplier

58(32−384)

vt_sys_clk_div

1 (1,2,4,6,8,10

12,14,16)

vt_pix_clk_div

6(4−16)

The maximum output of the parallel interface is 74.25

MPixel/s. The sensor will not use the FSERIAL,

FSERIAL_CLK, or CLK_OP when configured to use the

parallel interface.

Table 6. PLL PARAMETERS FOR THE PARALLEL INTERFACE

Parameter

Symbol

Min

Max

Unit

External Clock

EXTCLK

MHz

VCO Clock

FVCO

384

768

MHz

Output Clock

CLK_OP

74.25

Mpixel/s

Table 7. EXAMPLE PLL CONFIGURATION FOR THE PARALLEL INTERFACE

Parameter

Value

Output

FVCO

445.5 MHz (Max)

vt_sys_clk_div

vt_pix_clk_div

CLK_OP

74.25 MPixel/s (= 445.5 MHz / 6)

Output pixel rate

74.25 MPixel/s

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