AR0331 datasheet(46/52 Pages) ONSEMI

46 / 52 page

AR0331

www.onsemi.com

Table 29.

OPERATING CURRENT IN HiSPi (SLVS) OUTPUT AND LINEAR MODE (continued)

Definition

Unit

Max

Typ

Min

Symbol

Condition

PLL Supply Current

Streaming, 1080p60

IDD_PLL

–

SLVS Supply Current

Streaming, 1080p60

IDD_SLVS

–

1. Operating currents are measured at the following conditions:

VAA = VAA_PIX= VDD_PLL=2.8 V

VDD =VDD_IO= 1.8 V

VDD_SLVS = 0.4 V

PLL Enabled and PIXCLK=74.25 MHz

TA = 25°C

Table 30.

OPERATING CURRENT IN HiSPi (SLVS) OUTPUT AND HDR MODE

Definition

Condition

Symbol

Min

Typ

Max

Unit

Digital Operating Current

Streaming, 2048x1536 30fps

IDD

–

317

358

Analog Operating Current

Streaming, 2048x1536 30fps

IAA

–

Pixel Supply Current

Streaming, 2048x1536 30fps

IAA_PIX

–

PLL Supply Current

Streaming, 2048x1536 30fps

IDD_PLL

–

SLVS Supply Current

Streaming, 2048x1536 30fps

IDD_SLVS

–

Digital Operating Current

Streaming, 1080p60

IDD

–

323

358

Analog Operating Current

Streaming, 1080p60

IAA

–

Pixel Supply Current

Streaming, 1080p60

IAA_PIX

–

PLL Supply Current

Streaming, 1080p60

IDD_PLL

–

SLVS Supply Current

Streaming, 1080p60

IDD_SLVS

–

1. Operating currents are measured at the following conditions:

VAA=VAA_PIX= VDD_PLL=2.8 V

VDD = VDD_IO= 1.8 V

VDD_SLVS = 0.4 V

PLL Enabled and PIXCLK=74.25 MHz

TA = 25°C

HiSPi Electrical Specifications

The ON Semiconductor AR0331 sensor supports both

SLVS and HiVCM HiSPi modes. Please refer to the

High-Speed Serial Pixel (HiSPi) Interface Physical Layer

Specification

v2.00.00

for

electrical

definitions,

specifications, and timing information. The VDD_SLVS

supply in this datasheet corresponds to VDD_TX in the

HiSPi Physical Layer Specification. Similarly, VDD is

equivalent to VDD_HiSPi as referenced in the specification.

The DLL as implemented on AR0331 is limited in the

number of available delay steps and differs from the HiSPi

specification as described in this section.

Table 31.

CHANNEL SKEW

(Measurement Conditions: VDD_HiSPi = 1.8 V; VDD_HiSPi_TX = 0.8 V; Data Rate = 480 Mbps; DLL set to 0)

Data Lane Skew in Reference to Clock

tCHSKEW1PHY

−150

Table 32.

CLOCK DLL STEPS

(Measurement Conditions: VDD_HiSPi = 1.8 V; VDD_HiSPi_TX = 0.8 V; Data DLL set to 0)

Clock DLL Step

Delay at 660 Mbps

0.25

0.375

0.5

0.625

0.75

Eye_opening at 660 Mbps

0.85

0.78

0.71

0.69

1. The Clock DLL Steps 6 and 7 are not recommended by ON Semiconductor for the AR0331.

AR0331 Datasheet(PDF) 46 Page - ON Semiconductor

AR0331 Datasheet(HTML) 46 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

Datasheet Download

Link URL