 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AR0331 Datasheet(PDF) 41 Page - ON Semiconductor |
|
|
|||||||||||||||||||||||||||||
AR0331 Datasheet(HTML) 41 Page - ON Semiconductor |
|
|
41 / 52 page  AR0331 www.onsemi.com 41 ELECTRICAL SPECIFICATIONS Unless otherwise stated, the following specifications apply under the following conditions: • VDD = 1.8 V – 0.10/+0.15; VDD_IO = VDD_PLL = VAA = VAA_PIX = 2.8 V ±0.3 V; • VDD_SLVS = 0.4 V – 0.1/+0.2; TA = −30°C to +85°C; output load = 10 pF; • frequency = 74.25 MHz; HiSPi off. Two-Wire Serial Register Interface The electrical characteristics of the two-wire serial register interface (SCLK, SDATA) are shown in Figure 44 and Table 21. Figure 44. Two-Wire Serial Bus Timing Parameters S Sr tSU;STO tSU;STA tHD;STA tHIGH tLOW tSU;DAT tHD;DAT tf SDATA SCLK P S tBUF tr tf tr tHD;STA Note: Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register address are issued. Table 21. TWO−WIRE SERIAL BUS CHARACTERISTICS (fEXTCLK = 27 MHz; VDD = 1.8 V; VDD_IO = 2.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_PLL = 2.8 V; VDD_DAC = 2.8 V; TA = 25°C) Parameter Symbol Standard Mode Fast Mode Unit Min Max Min Max SCLK Clock Frequency fSCL 0 100 0 400 KHz Hold Time (Repeated) START Condition After this period, the first clock pulse is generated tHD;STA 4.0 − 0.6 − μS LOW Period of the SCLK Clock tLOW 4.7 − 1.3 − μS HIGH Period of the SCLK Clock tHIGH 4.0 − 0.6 − μS Set up Time for a Repeated START Condition tSU;STA 4.7 − 0.6 − μS Data Hold Time tHD;DAT 0 (Note 4) 3.45 (Note 5) 0 (Note 6) 0.9 (Note 5) μS Data Set-up Time tSU;DAT 250 − 100 (Note 6) − nS Rise Time of Both SDATA and SCLK Signals tr − 1000 20 + 0.1Cb (Note 7) 300 nS Fall Time of Both SDATA and SCLK Signals tf − 300 20 + 0.1Cb (Note 7) 300 nS Set-up Time for STOP Condition tSU;STO 4.0 − 0.6 − μS Bus Free Time between a STOP and START Condition tBUF 4.7 − 1.3 − μS Capacitive Load for Each bus Line Cb − 400 − 400 pF Serial Interface Input pin Capacitance CIN_SI − 3.3 − 3.3 pF SDATA Max Load Capacitance CLOAD_SD − 30 − 30 pF SDATA Pull-up Resistor RSD 1.5 4.7 1.5 4.7 KΩ 1. This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor. 2. Two-wire control is I2C-compatible. 3. All values referred to VIHmin = 0.9 VDD and VILmax = 0.1 VDD levels. Sensor EXCLK = 27 MHz. 4. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
