AR0331 datasheet(5/52 Pages) ONSEMI

5 / 52 page

AR0331

www.onsemi.com

Figure 3. Typical Configuration: Parallel Pixel Data Interface

Notes:

Master clock

(6–48 MHz)

SDATA

SCLK

RESET_BAR

TEST

FLASH

FRAME_VALID

SHUTTER

DOUT [11:0]

EXTCLK

DGND

Digital

ground

Analog

ground

Controller

LINE_VALID

PIXCLK

VAA_PIX

VDD_IO VDD

VDD_PLL VAA

VDD_IO

VDD

VDD_PLL

VAA

Digital I/0

Power1

Digital

Core

Power1

PLL

Power1

Analog

Power1

Analog

Power1

1. All power supplies should be adequately decoupled.

2. ON Semiconductor recommends a resistor value of 1.5 kΩ, but a greater value may be used for slower two-wire speed.

3. The serial interface output pads and VDDSLVS can be left unconnected if the parallel output interface is used.

4. ON Semiconductor recommends that 0.1 μF and 10 μF decoupling capacitors for each power supply are mounted as

close as possible to the pad. Actual values and results may vary depending on layout and design considerations. Refer

to the AR0331 demo headboard schematics for circuit recommendations.

5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital

power planes is minimized.

6. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents.

7. The EXTCLK input is limited to 6−48 MHz.

SADDR

OE_BAR

TRIGGER

AGND

From

Controller

VAA_PIX

AR0331 Datasheet(PDF) 5 Page - ON Semiconductor

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