EP7209 datasheet(13/128 Pages) CIRRUS

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EP7209

DS453PP2

2.2

Pin Descriptions

Table 4 describes the function of all the external signals to the EP7209. Note that all output signals are tri-

stateable to enable the Hi-Z test modes to be supported.

2.2.1

External Signal Functions

Function

Signal

Name

Signal

Description

Data bus

D[0:31]

I/O

32-bit system data bus for memory and I/O interface

Address bus

A[0:27]

28 bits of system byte address during memory and expansion cycles

Whenever the EP7209 is in the Standby State, the external address and data

buses are driven low. The RUN signal is used internally to force these buses to

be driven low. This is done to prevent peripherals that are powered-down from

draining current. Also, the internal peripheral’s signals get set to their Reset

State.

Memory

Interface

nMOE

Memory output enable, active low

nMWE

Memory write enable, active low

nCS[0:3]

Chip select; active low, SRAM-like chip selects for expansion

nCS[4:5]

Chip select; active low, CS for expansion or for CL-PS6700 select

EXPRDY

Expansion port ready; external expansion devices drive this low to extend the

bus cycle. This is used to insert wait states for an external bus cycle.

WRITE

Write strobe, low during reads, high during writes from the EP7209

WORD/

HALFWORD

To do write accesses of different sizes Word and Half-Word must be externally

decoded. The encoding of these signals is as follows:

The core will generate an address. When doing a read, the ARM core will

select the appropriate byte channels. When doing a write, the correct bytes

will have to be enabled depending on the above signals and the least signifi-

cant bits of the address bus.

The ARM architecture does not support unaligned accesses. For a read using

x 32 memory, it is assumed that you will ignore bits 1 and 0 of the address bus

and perform a word read (or in power critical systems decode the relevant bits

depending on the size of the access). If an unaligned read takes place, the

core will rotate the resulting data in the register. For more information on this

behavior see the LDR instruction in the ARM7TDMI data sheet.

EXPCLK

I/O

Expansion clock rate is the same as the CPU clock for 13 MHz and 18 MHz. It

runs at 36.864 MHz for 36,49 and 74 MHz modes; in 13 MHz mode this pin is

used as the clock input.

Table 4. External Signal Functions

Access Size

Word

Half-Word

Word

Half-Word

Byte

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