EP7209 datasheet(44/128 Pages) CIRRUS

44 / 128 page

EP7209

DS453PP2

terface is in use (PCMEN1 or PCMEN2 bits in the

SYSCON2 register are enabled). FBADDR should

never be programmed to 0x7 or 0x8, as these are

the locations for the on-chip Boot ROM and inter-

nal registers.

The screen is mapped to the video frame buffer as

one contiguous block where each horizontal line of

pixels is mapped to a set of consecutive bytes or

words in the video RAM. The video frame buffer

can be accessed word wide as pixel 0 is mapped to

the LSB in the buffer such that the pixels are ar-

ranged in a Little Endian manner.

The pixel bit rate, and hence the LCD refresh rate,

can be programmed from 18.432 MHz to 576 kHz

when operating in 18.432–73.728 MHz mode, or

13 MHz to 203 kHz when operating from a

13 MHz clock. The LCD controller is programmed

by writing to the LCD control register (LCDCON).

The LCDCON register should not be repro-

grammed while the LCD controller is enabled.

The LCD controller also contains two 32-bit palette

registers, which allow any 4-, 2-, or 1-bit pixel val-

ue to be mapped to any of the 15 gray scale values

available. The required DMA bandwidth to support

a ½ VGA panel displaying 4-bits-per-pixel data at

80 Hz

refresh

rate

approximately

6.2 Mbytes/sec. Assuming the frame buffer is

stored in a 32-bit wide the maximum theoretical

bandwidth

available

86 Mbytes/sec

36.864 MHz, or 29.7 Mbytes/sec at 13 MHz.

The LCD controller uses a nine stage 32-bit wide

FIFO to buffer display data. The LCD controller re-

quests new data when there are five words remain-

ing in the FIFO. This means that for a ½ VGA

display at 4-bits-per-pixel and 80 Hz refresh rate,

the maximum allowable DMA latency is approxi-

mately 3.25

µsec ((5 words x 8 bits/byte)/(640 x

240 x 4bpp x 80 Hz)) = 3.25

µsec). The worst-case

latency is the total number of cycles from when the

DMA request appears to when the first DMA data

word actually becomes available at the FIFO.

DMA has the highest priority, so it will always hap-

pen next in the system. The maximum number of

cycles required is 36 from the point at which the

DMA request occurs to the point at which the STM

is complete, then another 6 cycles before the data

actually arrives at the FIFO from the first DMA

read. This creates a total of 42 cycles. Assuming

the frame buffer is located in 32-bit wide, the worst

case latency is almost exactly 3.2

µs, with 13 MHz

page mode cycles. With each cycle consuming

~77 ns (i.e., 1/1 MHz), the value of 3.2

µs comes

from 42 cycles x 77 ns/cycle = ~3.23

µsec. If 16-bit

wide, then the worst case latency will double. In

this case, the maximum permissible display size

will be halved, to approx. 320 x 240 pixels, assum-

ing the same pixel depth and refresh rate has to be

maintained. If the frame buffer is to be stored in

static memory, then further calculations must be

performed. If 18 MHz mode is selected, and 32-bit

wide, then the worst case latency will be 2.26

µsec

(i.e., 42 cycles x 54 nsec/cycle). If 36 MHz mode is

selected, and 32-bit wide, then the worst case laten-

cy drops down to 1.49

µs. This calculation is a little

more complex for 36 MHz mode of operation. The

total number of cycles = (12 x 4) + 7 = 55. Thus, 55

27 ns = ~1.49

µsec.

Figure 11 shows the organization of the video map

for all combinations of bits per pixel.

The refresh rate is not affected by the number of

bits per pixel; however the LCD controller fetches

twice the data per refresh for 4-bits-per-pixel com-

pared to 2-bits-per-pixel. The main reason for re-

ducing the number of bits per pixel is to reduce the

power consumption of the memory where the video

frame buffer is mapped.

EP7209 Datasheet(PDF) 44 Page - Cirrus Logic

EP7209 Datasheet(HTML) 44 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL