EP7209 datasheet(32/128 Pages) CIRRUS

32 / 128 page

EP7209

DS453PP2

de-asserted, these port bits are available for GPIO.

When asserted, these port bits are used as the

PRDY signals. When the PRDY signal is de-assert-

ed (i.e., low), it indicates that the CL-PS6700 is

busy accessing its card. If a PC CARD access is at-

tempted while the device is busy, the PRDY signal

will cause the EP7209’s CPU to be stalled. The

EP7209’s CPU will have to wait for the card to be-

come available. DMA transfers to the LCD can still

continue in the background during this period of

time (as described below). The EP7209 can access

the registers in the CL-PS6700, regardless of the

state of the PRDY signal. If the EP7209 needs to

access the PC CARD via the CL-PS6700, it waits

until the PRDY signal is high before initiating a

transfer request. Once a request is sent, the PRDY

signal indicates if data is available.

In the case of a PC Card write, writes can be posted

to the CL-PS6700 device, with the same timing as

CL-PS6700 internal register writes. Writes will

normally be completed by the CL-PS6700 device

independent of the EP7209 processor activity. If a

posted write times out, or fails to complete for any

other reason, then the CL-PS6700 will issue an in-

terrupt (i.e., a WR_FAIL interrupt). In the case

where the CL-PS6700 write buffer is already full,

the PRDY signal will be de-asserted (i.e., driven

low) and the transaction will be stalled pending an

available slot in the buffer. In this case, the

EP7209’s CPU will be stalled until the write can be

posted successfully. While the PRDY signal is de-

asserted, the chip select to the CL-PS6700 will be

de-asserted and the main bus will be released so

that DMA transfers to the LCD controller can con-

tinue in the background.

In the case of a PC Card read, the PRDY signal

from the CL-PS6700 will be de-asserted until the

read data is ready. At this point, it will be reasserted

and the access will be completed in the same way

as for a register access. In the case of a byte access,

only one 16-bit data transfer will be required to

complete the access. While the PRDY signal is de-

asserted, the chip select to the CL-PS6700 will be

de-asserted and the main bus will be released so

that DMA transfers to the LCD controller can con-

tinue in the background.

The EP7209 will re-arbitrate for control of the bus

when the PRDY signal is reasserted to indicate that

the read or write transaction can be completed. The

CPU will always be stalled until the PC Card ac-

cess is completed.

A card read operation may be split into a request

cycle and a data cycle, or it may be combined into

a single request/data transfer cycle. This depends

on whether the data requested from the card is

available in the prefetch buffer (internal to the CL-

PS6700).

The request portion of the cycle, for a card read, is

similar to the request phase for a card write (de-

scribed above). If the requested data is available in

the prefetch buffer, the CL-PS6700 asserts the

PRDY signal before the rising edge of the third

clock and the EP7209 continues the cycle to read

the data. Otherwise, the PRDY signal is de-asserted

and the request cycle is stalled. The EP7209 may

Space Field Value

PC CARD Memory Space

Attribute

I/O

Common memory

CL-PS6700 registers

Table 16. Space Field Decoding

EP7209 Datasheet(PDF) 32 Page - Cirrus Logic

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