16-Bit, 250Msps, High-Dynamic-Performance,

Dual DAC with LVDS Inputs

14

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CMOS-Compatible Digital Inputs

Input Data Format Select (TORB)

The TORB input selects between two’s-complement or

offset binary digital input data. Set TORB to a CMOS-

logic-high level to indicate a two’s-complement input for-

mat. Set TORB to a CMOS-logic-low level to indicate a

binary input format.

Power-Down Operation (PD)

The MAX5878 also features an active-high power-down

mode that reduces the DAC’s digital current consump-

tion from 36.2mA to less than 5µA and the analog cur-

rent consumption from 84mA to less than 2µA. Set PD

high to power down the MAX5878. Set PD low for nor-

mal operation.

When powered down, the MAX5878 reduces the overall

power consumption to less than 16µW. The MAX5878

requires 10ms to wake up from power-down and enter

a fully operational state. The PD integrated pulldown

resistor activates the MAX5878 if PD is left floating.

Applications Information

CLK Interface

The MAX5878 features a flexible differential clock input

achieve optimum jitter performance. Use an ultra-low

jitter clock to achieve the required noise density. Clock

fied noise density. For that reason, the CLKP/CLKN

input source must be designed carefully. The differen-

tial clock (CLKN and CLKP) input can be driven from a

single-ended or a differential clock source. Differential

clock drive is required to achieve the best dynamic

performance from the DAC. For single-ended opera-

tion, drive CLKP with a low noise source and bypass

CLKN to GND with a 0.1µF capacitor.

Figure 6 shows a convenient and quick way to apply a

differential signal created from a single-ended source

(e.g., HP 8662A signal generator) and a wideband trans-

former. Alternatively, these inputs can be driven from a

CMOS-compatible clock source; however, it is recom-

mended to use sinewave or AC-coupled differential

ECL/PECL or LVDS drive for best dynamic performance.

110

Ω

TO

DECODE

LOGIC

D

D

Q

Q

B15P–B0P,

SELIQP

B15N–B0N,

SELIQN

CLOCK

MAX5878

Figure 5. Simplified LVDS-Compatible Digital Input Structure

DIGITAL INPUT CODE

OFFSET BINARY

TWO’S COMPLEMENT

OUT_P

OUT_N

0000 0000 0000 0000

1000 0000 0000 0000

0

0111 1111 1111 1111

0000 0000 0000 0000

1111 1111 1111 1111

0111 1111 1111 1111

0

Table 2. DAC Output Code Table

WIDEBAND RF TRANSFORMER

PERFORMS SINGLE-ENDED-TO-

DIFFERENTIAL CONVERSION

SINGLE-ENDED

CLOCK SOURCE

(e.g., HP 8662A)

GND

1:1

25

Ω

25

Ω

CLKP

CLKN

TO DAC

0.1

µF

0.1

µF

Figure 6. Differential Clock-Signal Generation