16-Bit, 250Msps, High-Dynamic-Performance,

Dual DAC with LVDS Inputs

4

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ELECTRICAL CHARACTERISTICS (continued)

put load 50

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Reference Input Compliance

Range

0.125

1.260

V

Reference Input Resistance

10

k

Ω

Reference Voltage Drift

±25

ppm/

°C

ANALOG OUTPUT TIMING (See Figure 4)

Output Fall Time

90% to 10% (Note 5)

0.7

ns

Output Rise Time

10% to 90% (Note 5)

0.7

ns

Output Propagation Delay

Excluding data latency (Note 5)

1.1

ns

Glitch Impulse

Measured differentially

1

30

Output Noise

30

pA/

√Hz

TIMING CHARACTERISTICS

Data to Clock Setup Time

Referenced to rising edge of clock (Note 6)

-1.2

ns

Data to Clock Hold Time

Referenced to rising edge of clock (Note 6)

2.0

ns

Latency to I output

9

Data Latency

Latency to Q output

8

Clock

Cycles

Minimum Clock Pulse-Width High

CLKP, CLKN

0.9

ns

Minimum Clock Pulse-Width Low

CLKP, CLKN

0.9

ns

LVDS LOGIC INPUTS (B15P/B15N–B0P/B0N, XORN, XORP, SELIQN, SELIQP)

Differential Input-Logic High

100

mV

Differential Input-Logic Low

-100

mV

Common-Mode Voltage Range

1.125

1.375

V

Differential Input Resistance

(Note 7)

110

Ω

Input Capacitance

2.5

pF

CMOS LOGIC INPUTS (PD, TORB)

Input-Logic High

0.7 x

V

Input-Logic Low

0.3 x

V

Input Leakage Current

-20

1

+20

µA

PD, TORB Internal Pulldown

Resistance

1.5

M

Ω

Input Capacitance

2.5

pF

CLOCK INPUTS (CLKP, CLKN)

Sine wave

>1.5

Differential Input

Voltage Swing

Square wave

>0.5