MPC9894 datasheet(2/28 Pages) ETC

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Advanced Clock Drivers Devices

Freescale Semiconductor

MPC9894

DEVICE DESCRIPTION

Figure 1. MPC9894 Block Diagram

Table 1. Pin Configurations

I/O

Type

Function

Supply

Active State

Clock Inputs and Outputs

CLK0, CLK0

CLK1, CLK1

CLK2, CLK2

CLK3, CLK3

Input

LVPECL

PLL reference clock inputs (differential)

(internal pulldown)

VDDIC

—

FB_IN, FB_IN

Input

LVPECL

PLL feedback signal input (differential). When configured for external

feedback, the QFB output should be connected to FB_IN. (internal

pulldown)

VDDIC

—

QA[1:0], QA[1:0]

Output

LVPECL

Bank A differential outputs

VDDAB

—

QB[1:0], QB[1:0]

Output

LVPECL

Bank B differential outputs

VDDAB

—

QC[1:0], QC[1:0]

Output

LVPECL

Bank C differential outputs

VDDCD

—

QD[1:0], QD[1:0]

Output

LVPECL

Bank D differential outputs

VDDCD

—

QFB, QFB

Output

LVPECL

Differential PLL feedback output. QFB must be connected to FB_IN for

correct operation

VDDCD

—

÷M/P

÷P

÷2, ÷4, ÷8, ÷16

IDCS

PLL

340 – 680 MHz

Comp

fcomp

I2C Interface

Control Logic

CLK0

FB_IN

CLK1

CLK2

CLK3

FB_IN

EX_FB_SEL

CLK_VALID[3:0]

CLK_ALARM_RST

PLL_BYPASS

SCL

SDA

ADDR[0:2]

MBOOT

MEDIA

PRESET

JTAG[4:0]

PLL_TST[2:0]

TPA

MSTROUT_EN

QA0

QA1

QB0

QB1

QC0

QC1

QD0

QD1

QFB

SEL_STAT[1:0]

INT

BUSY

LOCK

CLK_STAT[3:0]

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