MPC9894 datasheet(5/28 Pages) ETC

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Advanced Clock Drivers Devices

Freescale Semiconductor

MPC9894

OPERATING INFORMATION

Basic Functional Description

The MPC9894 is a quad-redundancy IDCS clock

generator. The redundancy feature allows automatic

switching from the reference clock source to a secondary

clock source on detection of a failed reference clock. The

MPC9894 will detect and report a missing clock on any of its

four inputs. Based upon the current IDCS mode setting and

the qualifier input pins, the MPC9894 will switch to the next

qualified secondary clock.

The input clock sources, CLK0, CLK1, CLK2, and CLK3,

are assumed to be the same frequency(1) but non-phase-

related sources. When a clock switch occurs, the phase

alignment to the new clock source will occur over an

extended time period, eliminating runt clock output pulses.

The maximum rate of phase change is specified in the AC

parameter Delta Period per Cycle(∆PER/CYC). The device

uses a fully integrated PLL to generate clock signals from

redundant clock sources. The PLL multiplies the input

reference clock signal by a variety of values, including 0.25,

0.5, 1, 2, 4 or 8. For a complete list refer to Table 9. The

frequency multiplied clock signal drives four independent

output banks. Each output bank is phase-aligned to the input

reference clock phase, providing virtually zero-delay

capability(2).

The configuration of the MPC9894 series of clock

generators is performed through either the I2C interface or by

the preset configuration mode. The I2C interface uses a 2 pin

interface to transmit clock and data to and from a series of

configuration and status registers in the MPC9894.

Definitions

IDCS:

Intelligent Dynamic Clock Switch. The IDCS monitors the

clock inputs CLK0, CLK1, CLK2, and CLK3. Upon a failure of

the reference clock signal, the IDCS switches to a qualified

secondary clock signal and the status flags are set.

Reference clock signal:

The input clock signal that is selected by the IDCS or

IDCS_MODE[2:0] as the input reference to the PLL.

Primary clock:

The input clock signal selected by IDCS_MODE[2:0]. The

primary clock may or may not be the reference clock,

depending on IDCS mode and IDCS status.

Secondary clock:

The input clock signal which will be selected by the IDCS

upon an automatic clock switch.

Tertiary, Quaternary clocks:

The input clock signals that will be selected by the IDCS,

in turn, after the current secondary clock. This clock selection

is based upon a round robin rotational sequence

Manual IDCS mode:

The reference clock input is selected by

IDCS_MODE[0xx].

Automatic IDCS mode:

The reference clock signal is determined by the IDCS.

Selected clock:

The SEL_STAT[1:0] flags indicate the reference clock

signal.

Qualified clock:

The corresponding CLK_VALID[3:0] signal is logic high,

the associated CLK_STAT status bit is logic high and no clock

failure is present.

Bit Ordering:

The bit ordering convention used in this document for both

pin and register documentation is NAME[7:0] where bit 7 is

the most significant bit and 0 is the least significant bit.

1. Refer to Table 39 for clock frequency specification.

2. Using external feedback.

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