MPC9894 datasheet(21/28 Pages) ETC

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Advanced Clock Drivers Devices

Freescale Semiconductor

MPC9894

VDD = 3.3 V ±5%, VDDAB,CD,IC = 3.3 V ±5% or VDDAB,CD,IC = 2.5 V ±5%

and PLL Lock

tLOCK

Maximum PLL Lock Time

µs

treset_ref

hold time on power up

treset_pulse

hold time

100

1. AC characteristics are design targets and pending characterization.

2. AC characteristics apply for parallel output termination of 50

Ω to VTT.

3. In bypass mode, the MPC9894 divides the input reference clock.

4. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fREF =(fVCO ÷ M) ⋅ N.

5. All Input Clock frequencies must be within this value to guarantee smooth phase transition on input clock switch.

6. VPP is the minimum differential input voltage swing required to maintain AC characteristics including tpd and device-to-device skew.

7. VPP, OK is the minimum differential input voltage swing required for a valid clock signal. Above VPP, OK the input will be detected as a good

clock (see IDCS).

8. VPP, NOK is the maximum differential input voltage swing for a guaranteed bad clock. Below VPP, NOK the input will be detected as a failed

clock (see IDCS).

9. VDDAB =VDDCD

10. Rate of period change is the maximum change of the clock output signal period T per cycle on a IDCS commanded switch.

11. Rate of period change is the maximum change of the clock output signal period T per cycle on a IDCS commanded switch.

12. –3 dB point of PLL transfer characteristics.

Table 39. AC Characteristics (TJ = –40°C to +110°C)(1) (2) (Continued)

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

Z=50

Ω

RT = 50

Ω

VTT

DUT MPC9894

Z=50

Ω

Differential

Pulse Generator

Z=50

Ω

RT = 50

Ω

VTT

Figure 7. MPC9894 AC Test Reference (Media = 0)

Figure 8 . MPC9894 AC Test Reference (Media = 1)

Z=50

Ω

RT = 100

Ω

DUT MPC9894

Z=50

Ω

Differential

Pulse Generator

Z=50

Ω

RT = 50

Ω

VTT

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