Advanced Clock Drivers Devices

12

Freescale Semiconductor

MPC9894

Output Configuration Register

The output configuration register is divided into four,

2 bit-groups with each group selecting the divide ratio for

output banks A through bank D, refer to Table 12. For each

bank, four output divider settings (

÷2, ÷4, ÷8, ÷16) are

available, refer to Table 12.

Mode Configuration Register

The mode configuration register, refer to Table 14, is a

read/write register and contains the fields for mode selection

as well as alarm reset.

The mode of the MPC9894 may be changed by writing the

three least significant Mode Configuration Register bits to the

desired value. The current idcs mode of the MPC9894 may

be obtained by reading this register.

The alarm reset bits, found in bit positions 6 thru 3, may be

used to individually reset the status flags of register 5. Each

of these flag bits are associated with the four clock inputs pins

and indicate a failed clock input. Clearing of a clock status

flag is performed by writing a logic 1 to the individual bit (or

bits if more than one flag is to be cleared). Care should be

taken to insure that the idcs mode information is written to the

proper value when resetting the clock status bits. The four

alarm reset bits always read as a logic 0. If a clock input

status flag is cleared and the clock input is still in a failed

state, the status flag will go set within 4 clock cycles after

being cleared.

Table 12. Output Configuration Register (Register 1 — Read/Write)

Bit

76543210

Description

FSEL_A[1:0]

FSEL_B[1:0]

FSEL_C[1:0]

FSEL_D[1:0]

Reset default

00000000

Preset default

00001010

Table 13. PLL Output Divider N (FSEL_A to FSEL_D)

FSEL_x[1:0]

Value

00

÷2

01

÷4

10

÷8

11

÷16

Table 14. Mode Configuration and Alarm Reset Register (Register 2 — Read/Write)

Bit

7

6

5

4

3

2

1

0

Description

not used

ALARM_RST[3:0] (Refer to Table 15)

IDCS_MODE[2:0] (Refer to Table 16)

Reset default

n/a

n/a

n/a

n/a

n/a

0

1

1

Preset default

n/a

n/a

n/a

n/a

n/a

1

0

0

Table 15. Individual Reset of CLK_STAT[x] Bits

ALARM_RST[x]

Description

0

No action

1

The status flag CLK_STAT[x] is cleared by setting of this bit. (bit always reads as zero)

1. This is a repeat of Table 8.

IDCS_MODE [2:0]

Description

Primary clock

2. For CLK_VALID[3:0] = 1111 and input clock validity.

000

Manual

CLK0

n/a

n/a

n/a

001

CLK1

n/a

n/a

n/a

010

CLK2

n/a

n/a

n/a

011

CLK3

n/a

n/a

n/a

100

Automatic

CLK0

CLK1

CLK2

CLK3

101

CLK1

CLK2

CLK3

CLK0

110

CLK2

CLK3

CLK0

CLK1

111

CLK3

CLK0

CLK1

CLK2