Advanced Clock Drivers Devices

Freescale Semiconductor

13

MPC9894

Device Configuration and Output Enable Register

The Device Configuration and Output Enable Register is

used to individually enable or disable each bank of outputs.

Output banks are enabled by setting the corresponding bit to

a logic 1 and disabled by setting the bit to a logic 0 as

described in Table 21. Output Clock Stop/Enable. The

disable logic sets the outputs of the addressed bank

synchronously to logic low state (Qx[] = 0 and Qx[] = 1). The

clock output enable/stop bits can be set asynchronous to any

clock signal without the risk of generating of runt pulses. The

PLL feedback output QFB cannot be disabled when

MPC9894 is configured for external feedback.

The Device Configuration Register, bit 6, QUAL_EN is

used to enable or disable all clock input qualifier pins.

Asserting this bit enables the Clock Qualifier Input Pins

CLK_VALID[3:0]. Deasserting this bit disables these pins

such that inputs on CLK_VALID[3:0] are ignored.

The INT_E bit, in bit position 7, is used to enable or disable

interrupts from occurring on the INT pin. The setting of the

interrupt flag (bit 7 of the Status Register) is unaffected by this

bit.

Table 17. Device Configuration and Output Clock Enable Register (Register 3 — Read/Write)

Bit

7

6

5

43

21

0

Description

INT_E

QUAL_EN

Slew_Control

Enable_QFB

ENABLE_QA

ENABLE_QB

ENABLE_QC

ENABLE_QD

Reset default

0

0

00

00

00

Preset default

1

1

00

11

11

Table 18. Interrupt Signal (INT) Enable INT_E

INT_E

Description

0

Interrupt signal INT is disabled

1

Interrupt signal INT is enabled

Table 19. Input Clock Qualifier Enable QUAL_EN

QUAL_EN

Description

0

CLK_VALID[3:0] are disabled (clock qualifier signals are disabled)

1

CLK_VALID[3:0] are enabled (clocks can be qualified)

Table 20. Slew Control

Slew_Control

Description

0

Clock slew direction on clock switch is toward the closest edge

1

Clock slew direction on clock switch is toward the lagging edge

Table 21. Output Clock Stop/Enable

ENABLE_Qx

Description

0

Output bank x is disabled (clock stop in logic low state)

1

Output bank x is enabled