MPC9894 datasheet(9/28 Pages) ETC

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Advanced Clock Drivers Devices

Freescale Semiconductor

MPC9894

CLOCK OUTPUT TRANSITION

An MPC9894 clock switch, either in IDCS manual or IDCS

automatic mode, follows the next positive edge of the newly

selected reference clock signal. The positive edge of the

feedback clock and the newly selected reference clock edge

will start to slew to alignment by adjusting the feedback edge

placement a small amount of time in each clock cycle.

Figure 2. Clock Switch shows a failed primary input clock with

the MPC9894 switching to and aligning to the secondary

clock. This small amount of additional time in each clock

cycle will ensure that the output clock does not have any

large phase changes or frequency changes in a short period

of time. The alignment will be to either 1) the closest edge,

either forward or backward or 2) toward the lagging clock

edge. The maximum rate of period change is specified in the

AC parameter tables with the parameter of ∆PER/CYC. This

parameter implies that the output clock edge will never

change more than the specified amount in any one cycle.

The busy signal is used to indicate that the MPC9894 is in

the process of slewing to the new input clock alignment. The

signal is accessed thru the BUSY pin and goes set upon a

clock switch. The pin is reset once the phase realignment is

completed. During the period that BUSY is active, the

configuration register of the MPC9894 should not be written

with new configuration data.

For example, if the current input clock of 62.5 MHz and the

secondary clock are 180 degrees out of phase then the

minimum clock transition time can be calculated by

tcycle =1 ÷ fcycle =1 ÷ 62.5 MHz = 16 ns

Therefore 180 degree clock difference is

tcycle ÷ 2 = 8 ns

Assuming a ∆PER/CYC of 40 ps, then

8ns

÷ 40 ps/cycle = 200 cycles.

This is the minimum number of cycles that will be required

for the alignment to the new clock. The alignment to the new

clock phase may occur slower than this but never faster.

The alignment on clock failure is selectable between either

1) the closest edge, either forward or backward or 2) toward

the lagging clock edge. The selection of the alignment

method is selected in the Slew_Control bit (bit 5) of the

Device Configuration and Output Enable Register. This

selection allows the user to select the alignment method that

best suits the application. The characteristics and

subsequent advantages and disadvantages of each method

are described as follows.

Slew to closest edge

The alignment is either forward toward the lagging

edge or backward toward the leading edge.

The alignment to the closest edge ensures

re-alignment to the new clock input in the minimum

time.

In applications where the input clocks are closely

aligned, there is no ambiguity on the direction of

clock slew.

The clock output frequency will either increase or

decrease based on direction of clock slew.

Slew to lagging edge

The output frequency always decreases. Thus the

clock frequency never violates a maximum

frequency specification in the user system.

When input clocks are closely aligned (within SPO

+ jitter) the MPC9894 may align to the closest edge

or to the lagging edge. In the case of multiple

MPC9894s with equivalent clock inputs one

MPC9894 may align in one direction while an other

MPC9894 may align to the opposite direction.

If default values for the Slew_Control is not the

configuration desired then the reconfiguration of the slew

method should be perform soon after power-up and the

configuration should remain fixed from that point.

BUSY

Output Clock

Secondary Clock

Primary Clock

BUSY

Figure 2. Clock Switch

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